From: Szabolcs Nagy <nsz@port70.net>
To: musl@lists.openwall.com
Subject: Re: clz instruction is unavailable for Thumb1
Date: Wed, 28 Feb 2018 11:43:05 +0100 [thread overview]
Message-ID: <20180228104305.GN4418@port70.net> (raw)
In-Reply-To: <CAJ86T=W95GF2U-Qs4D04abnoXwdkPQih0MwDAOQwPZv3uW7XBA@mail.gmail.com>
* Andre McCurdy <armccurdy@gmail.com> [2018-02-27 19:00:58 -0800]:
> On Tue, Feb 27, 2018 at 6:16 PM, Rich Felker <dalias@libc.org> wrote:
> > On Tue, Feb 27, 2018 at 05:26:13PM -0800, Andre McCurdy wrote:
> >> On Tue, Feb 27, 2018 at 5:01 PM, Rich Felker <dalias@libc.org> wrote:
> >> > I forget what the situation with v6-m is, and whether/how it could be
> >> > supportable. Is it really thumb1 or some thumb2 subset that fills
> >> > deficiencies?
> >>
> >> It's Thumb1 plus BL, DMB, DSB, ISB, MRS and MSR from Thumb2.
> >
> > So that covers barrier but not atomics or thread pointer or syscalls,
> > right?
>
> Thumb1 can make syscalls, but armv6-m has no atomics (the RTOS style
> alternative being to disable interrupts around critical sections) and
> no thread pointer (no coprocessors at all).
>
> > I'm not seeing how arm with only thumb1 plus the above can be a
> > viable platform musl could run on, but maybe there are some kernel
> > mechanisms to help..?
>
> I don't know if it's even possible to run a Linux kernel on these devices.
>
maybe this helps on linux:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=8fcd6c45f5a65621ec809b7866a3623e9a01d4ed
next prev parent reply other threads:[~2018-02-28 10:43 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-02-28 0:03 Zhao, Weiming
2018-02-28 0:37 ` Andre McCurdy
2018-02-28 1:01 ` Rich Felker
2018-02-28 1:26 ` Andre McCurdy
2018-02-28 2:16 ` Rich Felker
2018-02-28 3:00 ` Andre McCurdy
2018-02-28 10:43 ` Szabolcs Nagy [this message]
2018-02-28 3:56 ` Khem Raj
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