From mboxrd@z Thu Jan 1 00:00:00 1970 X-Msuck: nntp://news.gmane.org/gmane.linux.lib.musl.general/12759 Path: news.gmane.org!.POSTED!not-for-mail From: Rich Felker Newsgroups: gmane.linux.lib.musl.general Subject: Re: musl riscv port Date: Sun, 22 Apr 2018 22:51:46 -0400 Message-ID: <20180423025146.GZ3094@brightrain.aerifal.cx> References: <20180420200904.GS3094@brightrain.aerifal.cx> <0EC2E771-368F-454E-B08D-7D6A5321F598@mac.com> Reply-To: musl@lists.openwall.com NNTP-Posting-Host: blaine.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Trace: blaine.gmane.org 1524451796 32611 195.159.176.226 (23 Apr 2018 02:49:56 GMT) X-Complaints-To: usenet@blaine.gmane.org NNTP-Posting-Date: Mon, 23 Apr 2018 02:49:56 +0000 (UTC) User-Agent: Mutt/1.5.21 (2010-09-15) To: musl@lists.openwall.com Original-X-From: musl-return-12775-gllmg-musl=m.gmane.org@lists.openwall.com Mon Apr 23 04:49:52 2018 Return-path: Envelope-to: gllmg-musl@m.gmane.org Original-Received: from mother.openwall.net ([195.42.179.200]) by blaine.gmane.org with smtp (Exim 4.84_2) (envelope-from ) id 1fARY7-0008ON-F0 for gllmg-musl@m.gmane.org; Mon, 23 Apr 2018 04:49:51 +0200 Original-Received: (qmail 1666 invoked by uid 550); 23 Apr 2018 02:52:00 -0000 Mailing-List: contact musl-help@lists.openwall.com; run by ezmlm Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-ID: Original-Received: (qmail 1623 invoked from network); 23 Apr 2018 02:51:59 -0000 Content-Disposition: inline In-Reply-To: <0EC2E771-368F-454E-B08D-7D6A5321F598@mac.com> Original-Sender: Rich Felker Xref: news.gmane.org gmane.linux.lib.musl.general:12759 Archived-At: On Mon, Apr 23, 2018 at 09:40:08AM +1200, Michael Clark wrote: > BTW - I owe you an update on the riscv musl port. I’ll post one > soon.... I’ve been busy on the QEMU RISC-V port, whose ‘virt’ board > has recently been used by Fedora and Debian distro porters for > riscv64 arch support (glibc based distros). Stefan O’Rear got MTTCG > working on qemu/target/riscv so we can run SMP Linux in QEMU with > reasonable performance. Debian for example now has QEMU RISC-V > builders for the riscv64 arch. > > - https://github.com/riscv/riscv-qemu/wiki > > It will be nice to get the riscv musl support upstream. The major > issue at present is ELF thread local storage (pthreads are working > but GCC’s __thread is not). The RISC-V TLS model is not documented > so it requires some reverse engineering of the riscv support in > GCC/binutils/glibc. I haven’t been able to isolate the issue and > could benefit from some help by someone more knowledgable in that > area (ELF TLS and architecture specific TLS models). If you have specific questions here I can probably help you find answers quickly. It probably suffices just to compile and link a trivial test program using a single TLS variable, and see what offset from the thread pointer the compiler accesses it at. That should tell you if TLS is above or below the thread pointer, and if there's any offset that needs to be applied, what it is. Once it's all working, the big thing that might take some additional effort to get it merged is making sure contributions have been documented. I know a bunch of different people worked on this on and off and I want to make sure they all get credited properly. Rich