From mboxrd@z Thu Jan 1 00:00:00 1970 X-Msuck: nntp://news.gmane.org/gmane.linux.lib.musl.general/12799 Path: news.gmane.org!.POSTED!not-for-mail From: Rich Felker Newsgroups: gmane.linux.lib.musl.general Subject: Re: Some questions Date: Wed, 2 May 2018 09:42:24 -0400 Message-ID: <20180502134224.GW1392@brightrain.aerifal.cx> References: <20180430031653.GI1392@brightrain.aerifal.cx> <20180430153112.GL1392@brightrain.aerifal.cx> <20180501155233.GS1392@brightrain.aerifal.cx> <20180501173535.GT1392@brightrain.aerifal.cx> <20180501221441.GX4418@port70.net> Reply-To: musl@lists.openwall.com NNTP-Posting-Host: blaine.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Trace: blaine.gmane.org 1525268436 8620 195.159.176.226 (2 May 2018 13:40:36 GMT) X-Complaints-To: usenet@blaine.gmane.org NNTP-Posting-Date: Wed, 2 May 2018 13:40:36 +0000 (UTC) User-Agent: Mutt/1.5.21 (2010-09-15) Cc: Patrick Oppenlander To: musl@lists.openwall.com Original-X-From: musl-return-12815-gllmg-musl=m.gmane.org@lists.openwall.com Wed May 02 15:40:32 2018 Return-path: Envelope-to: gllmg-musl@m.gmane.org Original-Received: from mother.openwall.net ([195.42.179.200]) by blaine.gmane.org with smtp (Exim 4.84_2) (envelope-from ) id 1fDrzk-00028y-1x for gllmg-musl@m.gmane.org; Wed, 02 May 2018 15:40:32 +0200 Original-Received: (qmail 15882 invoked by uid 550); 2 May 2018 13:42:37 -0000 Mailing-List: contact musl-help@lists.openwall.com; run by ezmlm Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-ID: Original-Received: (qmail 15838 invoked from network); 2 May 2018 13:42:37 -0000 Content-Disposition: inline In-Reply-To: <20180501221441.GX4418@port70.net> Original-Sender: Rich Felker Xref: news.gmane.org gmane.linux.lib.musl.general:12799 Archived-At: On Wed, May 02, 2018 at 12:14:41AM +0200, Szabolcs Nagy wrote: > * Andre McCurdy [2018-05-01 14:49:00 -0700]: > > On Tue, May 1, 2018 at 10:35 AM, Rich Felker wrote: > > > I'm considering applying the attached patch, which would make it so > > > VLAs don't break thumb syscalls and eliminate the need to force frame > > > pointer off when building as thumb. This is all a workaround for gcc > > > being wrong about not letting you use r7, but it seems reasonable and > > > non-invasive. It just omits r7 from the constraints and uses a temp > > > register to save/restore it. > > > > This seems to fail when compiling src/thread/arm/__set_thread_area.c: > > > > {standard input}: Assembler messages: > > {standard input}:45: Error: invalid constant (f0005) after fixup > > make: *** [obj/src/thread/arm/__set_thread_area.o] Error 1 > > > > Without the patch, __set_thread_area() effectively compiles to: > > > > __set_thread_area: > > push {r7, lr} > > ldr r7, .L2 > > pop {r7, pc} > > .L2: > > .word 983045 > > > > With the patch: > > > > __set_thread_area: > > push {r7, lr} > > add r7, sp, #0 > > mov r3,r7 ; mov r7,#983045 ; svc 0 ; mov r7,r3 > > pop {r7, pc} > > > > ie the immediate value 0xf0005 can't be loaded directly into r7 with a > > single Thumb2 mov instruction. > > > > I tried a quick test to replace the single mov instruction in > > __asm_syscall() with a movw + movt pair: > > > > i think the syscall can be just inline asm here, > since __set_thread_area is arm specific code. > > in generic code the mov r7,.. hack should work > and fixes the vla issue. > > (alternatively using just "r" operand instead > of "rI" does not generate immediate, but will > use more registers/instructions) The above posted patch used "ri" not "rI". The "I" constraint, which I switched to after posting the patch, only allows immediates that work with mov, so the issue does not arise. Rich