From mboxrd@z Thu Jan 1 00:00:00 1970 X-Msuck: nntp://news.gmane.org/gmane.linux.lib.musl.general/14717 Path: news.gmane.org!.POSTED.blaine.gmane.org!not-for-mail From: Palmer Dabbelt Newsgroups: gmane.linux.lib.musl.general Subject: [PATCH] correct the operand specifiers in the riscv64 CAS routines Date: Tue, 24 Sep 2019 20:30:15 -0700 Message-ID: <20190925033015.9905-1-palmer@sifive.com> Reply-To: musl@lists.openwall.com Mime-Version: 1.0 Content-Transfer-Encoding: 8bit Injection-Info: blaine.gmane.org; posting-host="blaine.gmane.org:195.159.176.226"; logging-data="112729"; mail-complaints-to="usenet@blaine.gmane.org" Cc: Alistair Francis , Palmer Dabbelt To: musl@lists.openwall.com Original-X-From: musl-return-14733-gllmg-musl=m.gmane.org@lists.openwall.com Wed Sep 25 05:35:20 2019 Return-path: Envelope-to: gllmg-musl@m.gmane.org Original-Received: from mother.openwall.net ([195.42.179.200]) by blaine.gmane.org with smtp (Exim 4.89) (envelope-from ) id 1iCy5H-000TDw-UU for gllmg-musl@m.gmane.org; Wed, 25 Sep 2019 05:35:20 +0200 Original-Received: (qmail 2002 invoked by uid 550); 25 Sep 2019 03:35:17 -0000 Mailing-List: contact musl-help@lists.openwall.com; run by ezmlm Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-ID: Original-Received: (qmail 1970 invoked from network); 25 Sep 2019 03:35:16 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=subject:date:message-id:mime-version:content-transfer-encoding:cc :from:to; bh=Ih7mYEDymy7zm/SgdV5prQBTDtSd1esE9Qy24D4sxHY=; b=E6adHYFbUkiaJbJxbWE/sRUTfEHytB9i9k/Rqb8wkTDAsZ4IA6RZPdx3Vca+4TqUZF Ge0AvxJWncTgQrz48J6qAgNeGuLCE8Vl5leSIrZkfFPsNgffvmsOjxvlXKn2J+7wNOub LQg7G/UpEbdlmjxvrWh1pcNcSvs2TDI/3ExnRFT9Qi24oDznFke8i48FvAkgTA4K4jI9 uiWWhSSIdKL2N/ksEXGmVt0mHq3C3szZkWeP9kESU/LDSFhiBcxnvDody1eadiGrxW7K DxwH0sOP4gAL25XOoQjfSKquLd1raKLFs+jh6QU/Xx1q4RHfmXqMt1EapMFiF4eWpDnG cEsg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:mime-version :content-transfer-encoding:cc:from:to; bh=Ih7mYEDymy7zm/SgdV5prQBTDtSd1esE9Qy24D4sxHY=; b=S0vCMDksytXX+u0T1Cuzh2wsYvUL1PCYIry+U88ih+66CZJ1qgpBiTfBfx2Rf6KLBo eleo2ZO0niDR0l4kzyGcTxYU6Nvz+D6Rt+lGNqusZH4juP/ayZGIHscP627pub7PYMV4 UE5d29pgyJyhx02OCnbqo1ruCI7W+BfzfTE1SL5fu8sV2Qx5keooMASBe3G+/AzRZB3t fRcTfrtq4f3ED2a1WLy7YTjSJdLWRAiqCTUw6f4do/aROOF7NntF9HK2VdoSRlDR8QgG B8VQFIXHpomz8DMNJyqCWokLy5ByXH2+k0x3jQQjbnXry3xI6ILzJGIuZMgLcHeH08Cv Pnog== X-Gm-Message-State: APjAAAWbec1pSggBIW85mYR1DeSmuuXid54oYAfEKD0FEoY+G6GP39ud wQetD73JgiNe8fnFaSZCJnV7/Q== X-Google-Smtp-Source: APXvYqy9CrBxqBLMgKV0Q5GOx4foRNlv1XTYYdgJAMmm8XM6iLgBAx7bL7S5JBtWgd3CmDGRlJsRyA== X-Received: by 2002:aa7:8009:: with SMTP id j9mr7150263pfi.107.1569382504343; Tue, 24 Sep 2019 20:35:04 -0700 (PDT) X-Mailer: git-send-email 2.21.0 Xref: news.gmane.org gmane.linux.lib.musl.general:14717 Archived-At: The operand sepcifiers in a_cas and a_casp for riscv64 were incorrect: there's a backwards branch in the routine, so despite tmp being written at the end of the assembly fragment it cannot be allocated in one of the input registers because the input values may be needed for another trip around the loop. For code that follows the guarnteed forward progress requirements, he backwards branch is rarely taken: SiFive's hardware only fails a store conditional on execptional cases (ie, instruction cache misses inside the loop), and until recently a bug in QEMU allowed back-to-back store conditionals to succeed. The bug has been fixed in the latest QEMU release, but it turns out that the fix caused this latent bug in musl to manifest. Full disclosure: I haven't actually even compiled musl. I just guessed this would fix a bug introducted by the new QEMU behavior, Alistair (CC'd) actually checked it fixes the problem. The rest is just conjecture. --- arch/riscv64/atomic_arch.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/riscv64/atomic_arch.h b/arch/riscv64/atomic_arch.h index c976534284aa..41ad4d04907c 100644 --- a/arch/riscv64/atomic_arch.h +++ b/arch/riscv64/atomic_arch.h @@ -14,7 +14,7 @@ static inline int a_cas(volatile int *p, int t, int s) " sc.w.aqrl %1, %4, (%2)\n" " bnez %1, 1b\n" "1:" - : "=&r"(old), "=r"(tmp) + : "=&r"(old), "=&r"(tmp) : "r"(p), "r"(t), "r"(s) : "memory"); return old; @@ -31,7 +31,7 @@ static inline void *a_cas_p(volatile void *p, void *t, void *s) " sc.d.aqrl %1, %4, (%2)\n" " bnez %1, 1b\n" "1:" - : "=&r"(old), "=r"(tmp) + : "=&r"(old), "=&r"(tmp) : "r"(p), "r"(t), "r"(s) : "memory"); return old; -- 2.21.0