From mboxrd@z Thu Jan 1 00:00:00 1970 X-Msuck: nntp://news.gmane.org/gmane.linux.lib.musl.general/14737 Path: news.gmane.org!.POSTED.blaine.gmane.org!not-for-mail From: Rich Felker Newsgroups: gmane.linux.lib.musl.general Subject: Re: mips fp32/fpxx/fp64 issues, r6 sjlj broken Date: Thu, 26 Sep 2019 19:23:50 -0400 Message-ID: <20190926232350.GD9017@brightrain.aerifal.cx> References: <20190926224520.GC9017@brightrain.aerifal.cx> Reply-To: musl@lists.openwall.com Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="juwRYO7N74otsfNI" Injection-Info: blaine.gmane.org; posting-host="blaine.gmane.org:195.159.176.226"; logging-data="61068"; mail-complaints-to="usenet@blaine.gmane.org" User-Agent: Mutt/1.5.21 (2010-09-15) To: musl@lists.openwall.com Original-X-From: musl-return-14753-gllmg-musl=m.gmane.org@lists.openwall.com Fri Sep 27 01:24:06 2019 Return-path: Envelope-to: gllmg-musl@m.gmane.org Original-Received: from mother.openwall.net ([195.42.179.200]) by blaine.gmane.org with smtp (Exim 4.89) (envelope-from ) id 1iDd7G-000FnY-Pu for gllmg-musl@m.gmane.org; Fri, 27 Sep 2019 01:24:06 +0200 Original-Received: (qmail 19816 invoked by uid 550); 26 Sep 2019 23:24:04 -0000 Mailing-List: contact musl-help@lists.openwall.com; run by ezmlm Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-ID: Original-Received: (qmail 19796 invoked from network); 26 Sep 2019 23:24:03 -0000 Content-Disposition: inline In-Reply-To: <20190926224520.GC9017@brightrain.aerifal.cx> Original-Sender: Rich Felker Xref: news.gmane.org gmane.linux.lib.musl.general:14737 Archived-At: --juwRYO7N74otsfNI Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Thu, Sep 26, 2019 at 06:45:21PM -0400, Rich Felker wrote: > Also, mipsr6 (the new mips-family ISA that's not compatible with > previous mips) always uses the 64-bit register mode. We presently do > not have setjmp/longjmp code that works with this case at all > (existing code will wrongly save low 32-bits of 2 registers instead of > single whole double register); somehow nobody has noticed that this is > broken. Making this conditional on __mips_isa_rev >= 6 should not be > hard. Attached patch should work, but maybe isn't the best thing to do. I think using sdc1/ldc1 and just even indices like on r6 would also be valid for pre-r6 mips using fp32 or fpxx abi; with FR=0, it would save/restore the pair of 32-bit registers, and with FR=1, fp32 code could not be running anyway, and fpxx code should work fine. However, mips I lacks the ldc1/stc1 instructions, so at the very least we'd need to leave the old form in place for mips I. Or maybe use the s.d and l.d mnemonics that automatically assemble to the right choice based on the isa level... BTW, the document I linked in the previous email mentions stuff about setjmp having to align float args section at runtime, but that does not seem relevant since the jmp_buf has always been 64-bit aligned, so I didn't do anything like that. glibc doesn't either. Rich --juwRYO7N74otsfNI Content-Type: text/plain; charset=us-ascii Content-Disposition: attachment; filename="mips-sjlj.diff" diff --git a/src/setjmp/mips/longjmp.S b/src/setjmp/mips/longjmp.S index fdb6c95d..162646b6 100644 --- a/src/setjmp/mips/longjmp.S +++ b/src/setjmp/mips/longjmp.S @@ -12,6 +12,14 @@ longjmp: addu $2, $2, 1 1: #ifndef __mips_soft_float +#if __mips_isa_rev >= 6 + ldc1 $20, 56($4) + ldc1 $22, 64($4) + ldc1 $24, 72($4) + ldc1 $26, 80($4) + ldc1 $28, 88($4) + ldc1 $30, 96($4) +#else lwc1 $20, 56($4) lwc1 $21, 60($4) lwc1 $22, 64($4) @@ -24,6 +32,7 @@ longjmp: lwc1 $29, 92($4) lwc1 $30, 96($4) lwc1 $31, 100($4) +#endif #endif lw $ra, 0($4) lw $sp, 4($4) diff --git a/src/setjmp/mips/setjmp.S b/src/setjmp/mips/setjmp.S index 501d5264..c2700bcb 100644 --- a/src/setjmp/mips/setjmp.S +++ b/src/setjmp/mips/setjmp.S @@ -22,6 +22,14 @@ setjmp: sw $30, 40($4) sw $28, 44($4) #ifndef __mips_soft_float +#if __mips_isa_rev >= 6 + sdc1 $20, 56($4) + sdc1 $22, 64($4) + sdc1 $24, 72($4) + sdc1 $26, 80($4) + sdc1 $28, 88($4) + sdc1 $30, 96($4) +#else swc1 $20, 56($4) swc1 $21, 60($4) swc1 $22, 64($4) @@ -34,6 +42,7 @@ setjmp: swc1 $29, 92($4) swc1 $30, 96($4) swc1 $31, 100($4) +#endif #endif jr $ra li $2, 0 --juwRYO7N74otsfNI--