From mboxrd@z Thu Jan 1 00:00:00 1970 X-Msuck: nntp://news.gmane.org/gmane.linux.lib.musl.general/14973 Path: news.gmane.org!.POSTED.blaine.gmane.org!not-for-mail From: Ruinland ChuanTzu Tsai Newsgroups: gmane.linux.lib.musl.general Subject: [PATCH] riscv64: fenv.S: Fix fesetenv(FE_DFL_ENV) failure Date: Mon, 2 Dec 2019 19:06:52 +0800 Message-ID: <20191202110648.GA3068@APC301.andestech.com> Reply-To: musl@lists.openwall.com Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Injection-Info: blaine.gmane.org; posting-host="blaine.gmane.org:195.159.176.226"; logging-data="259843"; mail-complaints-to="usenet@blaine.gmane.org" User-Agent: Mutt/1.9.4 (2018-02-28) Cc: To: Original-X-From: musl-return-14989-gllmg-musl=m.gmane.org@lists.openwall.com Mon Dec 02 12:07:20 2019 Return-path: Envelope-to: gllmg-musl@m.gmane.org Original-Received: from mother.openwall.net ([195.42.179.200]) by blaine.gmane.org with smtp (Exim 4.89) (envelope-from ) id 1ibjXz-0015NK-BI for gllmg-musl@m.gmane.org; Mon, 02 Dec 2019 12:07:19 +0100 Original-Received: (qmail 24138 invoked by uid 550); 2 Dec 2019 11:07:16 -0000 Mailing-List: contact musl-help@lists.openwall.com; run by ezmlm Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-ID: Original-Received: (qmail 24103 invoked from network); 2 Dec 2019 11:07:15 -0000 Content-Disposition: inline X-Originating-IP: [10.0.12.139] X-MAIL: ATCSQR.andestech.com xB2B710k016833 Xref: news.gmane.org gmane.linux.lib.musl.general:14973 Archived-At: Hi all, during testing libc-test on RV64, I happended to encounter a segfault on math/fenv.exe . When FE_DFL_ENV is passed to fesetenv(), the very first instruction : lw t1, 0(a0) will fail since a0 is -1 . Here's quick hack - - git diff -- src/fenv/riscv64/fenv.S diff --git a/src/fenv/riscv64/fenv.S b/src/fenv/riscv64/fenv.S index 97f74dd6..06215954 100644 --- a/src/fenv/riscv64/fenv.S +++ b/src/fenv/riscv64/fenv.S @@ -45,8 +45,12 @@ fegetenv: .global fesetenv .type fesetenv, %function fesetenv: + li t2, -1 + li t1, 0 + beq a0, t2, setfpcsr lw t1, 0(a0) - fscsr t0, t1 +setfpcsr: + fscsr t1 li a0, 0 ret And the test case will pass. Sincerely, Ruinland Chuan-Tzu Tsai