* [PATCH] riscv64: fenv.S: Fix fesetenv(FE_DFL_ENV) failure
@ 2019-12-02 11:06 Ruinland ChuanTzu Tsai
2019-12-02 16:46 ` Szabolcs Nagy
2019-12-07 18:00 ` Rich Felker
0 siblings, 2 replies; 3+ messages in thread
From: Ruinland ChuanTzu Tsai @ 2019-12-02 11:06 UTC (permalink / raw)
To: musl; +Cc: alankao
Hi all,
during testing libc-test on RV64,
I happended to encounter a segfault on math/fenv.exe .
When FE_DFL_ENV is passed to fesetenv(),
the very first instruction : lw t1, 0(a0)
will fail since a0 is -1 .
Here's quick hack - -
git diff -- src/fenv/riscv64/fenv.S
diff --git a/src/fenv/riscv64/fenv.S b/src/fenv/riscv64/fenv.S
index 97f74dd6..06215954 100644
--- a/src/fenv/riscv64/fenv.S
+++ b/src/fenv/riscv64/fenv.S
@@ -45,8 +45,12 @@ fegetenv:
.global fesetenv
.type fesetenv, %function
fesetenv:
+ li t2, -1
+ li t1, 0
+ beq a0, t2, setfpcsr
lw t1, 0(a0)
- fscsr t0, t1
+setfpcsr:
+ fscsr t1
li a0, 0
ret
And the test case will pass.
Sincerely,
Ruinland Chuan-Tzu Tsai
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH] riscv64: fenv.S: Fix fesetenv(FE_DFL_ENV) failure
2019-12-02 11:06 [PATCH] riscv64: fenv.S: Fix fesetenv(FE_DFL_ENV) failure Ruinland ChuanTzu Tsai
@ 2019-12-02 16:46 ` Szabolcs Nagy
2019-12-07 18:00 ` Rich Felker
1 sibling, 0 replies; 3+ messages in thread
From: Szabolcs Nagy @ 2019-12-02 16:46 UTC (permalink / raw)
To: musl; +Cc: alankao
* Ruinland ChuanTzu Tsai <ruinland@andestech.com> [2019-12-02 19:06:52 +0800]:
> Hi all,
> during testing libc-test on RV64,
> I happended to encounter a segfault on math/fenv.exe .
>
> When FE_DFL_ENV is passed to fesetenv(),
> the very first instruction : lw t1, 0(a0)
> will fail since a0 is -1 .
>
> Here's quick hack - -
>
> git diff -- src/fenv/riscv64/fenv.S
> diff --git a/src/fenv/riscv64/fenv.S b/src/fenv/riscv64/fenv.S
> index 97f74dd6..06215954 100644
> --- a/src/fenv/riscv64/fenv.S
> +++ b/src/fenv/riscv64/fenv.S
> @@ -45,8 +45,12 @@ fegetenv:
> .global fesetenv
> .type fesetenv, %function
> fesetenv:
> + li t2, -1
> + li t1, 0
> + beq a0, t2, setfpcsr
> lw t1, 0(a0)
> - fscsr t0, t1
> +setfpcsr:
> + fscsr t1
> li a0, 0
> ret
>
> And the test case will pass.
thanks, this looks good
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] riscv64: fenv.S: Fix fesetenv(FE_DFL_ENV) failure
2019-12-02 11:06 [PATCH] riscv64: fenv.S: Fix fesetenv(FE_DFL_ENV) failure Ruinland ChuanTzu Tsai
2019-12-02 16:46 ` Szabolcs Nagy
@ 2019-12-07 18:00 ` Rich Felker
1 sibling, 0 replies; 3+ messages in thread
From: Rich Felker @ 2019-12-07 18:00 UTC (permalink / raw)
To: musl
On Mon, Dec 02, 2019 at 07:06:52PM +0800, Ruinland ChuanTzu Tsai wrote:
> Hi all,
> during testing libc-test on RV64,
> I happended to encounter a segfault on math/fenv.exe .
>
> When FE_DFL_ENV is passed to fesetenv(),
> the very first instruction : lw t1, 0(a0)
> will fail since a0 is -1 .
>
> Here's quick hack - -
>
> git diff -- src/fenv/riscv64/fenv.S
> diff --git a/src/fenv/riscv64/fenv.S b/src/fenv/riscv64/fenv.S
> index 97f74dd6..06215954 100644
> --- a/src/fenv/riscv64/fenv.S
> +++ b/src/fenv/riscv64/fenv.S
> @@ -45,8 +45,12 @@ fegetenv:
> .global fesetenv
> .type fesetenv, %function
> fesetenv:
> + li t2, -1
> + li t1, 0
> + beq a0, t2, setfpcsr
> lw t1, 0(a0)
> - fscsr t0, t1
> +setfpcsr:
> + fscsr t1
> li a0, 0
> ret
>
> And the test case will pass.
Looks mostly ok. Applying without the label name, 1f/1: instead. I was
a bit confused by the removal of the t0 operand from fscsr but
apparently the one-operand form implicitly uses the zero register as
rd.
Rich
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2019-12-07 18:00 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
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2019-12-02 11:06 [PATCH] riscv64: fenv.S: Fix fesetenv(FE_DFL_ENV) failure Ruinland ChuanTzu Tsai
2019-12-02 16:46 ` Szabolcs Nagy
2019-12-07 18:00 ` Rich Felker
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