Re: [PATCH] riscv64: fenv.S: Fix fesetenv(FE_DFL_ENV) failure

[Rich Felker <dalias@libc.org>]

On Mon, Dec 02, 2019 at 07:06:52PM +0800, Ruinland ChuanTzu Tsai wrote:
> Hi all, 
> during testing libc-test on RV64,
> I happended to encounter a segfault on math/fenv.exe .
> 
> When FE_DFL_ENV is passed to fesetenv(),
> the very first instruction : lw t1, 0(a0) 
> will fail since a0 is -1 .
> 
> Here's quick hack - -
> 
> git diff -- src/fenv/riscv64/fenv.S
> diff --git a/src/fenv/riscv64/fenv.S b/src/fenv/riscv64/fenv.S
> index 97f74dd6..06215954 100644
> --- a/src/fenv/riscv64/fenv.S
> +++ b/src/fenv/riscv64/fenv.S
> @@ -45,8 +45,12 @@ fegetenv:
>  .global fesetenv
>  .type fesetenv, %function
>  fesetenv:
> +        li t2, -1
> +        li t1, 0
> +        beq a0, t2, setfpcsr
>          lw t1, 0(a0)
> -        fscsr t0, t1
> +setfpcsr:
> +        fscsr t1
>          li a0, 0
>          ret
> 
> And the test case will pass.

Looks mostly ok. Applying without the label name, 1f/1: instead. I was
a bit confused by the removal of the t0 operand from fscsr but
apparently the one-operand form implicitly uses the zero register as
rd.

Rich