From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on inbox.vuxu.org X-Spam-Level: X-Spam-Status: No, score=-3.0 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED,RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL autolearn=ham autolearn_force=no version=3.4.2 Received: from mother.openwall.net (mother.openwall.net [195.42.179.200]) by inbox.vuxu.org (OpenSMTPD) with SMTP id a755482a for ; Sat, 18 Jan 2020 16:51:56 +0000 (UTC) Received: (qmail 26607 invoked by uid 550); 18 Jan 2020 16:51:54 -0000 Mailing-List: contact musl-help@lists.openwall.com; run by ezmlm Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-ID: Reply-To: musl@lists.openwall.com Received: (qmail 26589 invoked from network); 18 Jan 2020 16:51:54 -0000 Date: Sat, 18 Jan 2020 17:51:42 +0100 From: Szabolcs Nagy To: musl@lists.openwall.com Message-ID: <20200118165142.GG23985@port70.net> Mail-Followup-To: musl@lists.openwall.com References: <20200118161516.22758-1-amonakov@ispras.ru> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200118161516.22758-1-amonakov@ispras.ru> User-Agent: Mutt/1.10.1 (2018-07-13) Subject: Re: [musl] [PATCH] math/x32: correct lrintl.s for 32-bit long * Alexander Monakov [2020-01-18 19:15:16 +0300]: > --- > Looks like the implementation copied from x86_64 was not adjusted for > 32-bit 'long' on x32, but apart from failure to raise FE_INVALID this > error was harmless. fenv behaviour is wrong on out-of-range values, not just because of missing invalid, but spurious inexact too. thanks for finding this. > > src/math/x32/lrintl.s | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/src/math/x32/lrintl.s b/src/math/x32/lrintl.s > index ee97d1cf..d4355c32 100644 > --- a/src/math/x32/lrintl.s > +++ b/src/math/x32/lrintl.s > @@ -2,6 +2,6 @@ > .type lrintl,@function > lrintl: > fldt 8(%esp) > - fistpll 8(%esp) > - mov 8(%esp),%rax > + fistpl 8(%esp) > + movl 8(%esp),%eax > ret