From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on inbox.vuxu.org X-Spam-Level: X-Spam-Status: No, score=-2.4 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED,RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL,SUBJ_OBFU_PUNCT_FEW autolearn=ham autolearn_force=no version=3.4.2 Received: from mother.openwall.net (mother.openwall.net [195.42.179.200]) by inbox.vuxu.org (OpenSMTPD) with SMTP id a27c795f for ; Fri, 24 Jan 2020 03:27:41 +0000 (UTC) Received: (qmail 11380 invoked by uid 550); 24 Jan 2020 03:27:39 -0000 Mailing-List: contact musl-help@lists.openwall.com; run by ezmlm Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-ID: Reply-To: musl@lists.openwall.com Received: (qmail 11360 invoked from network); 24 Jan 2020 03:27:39 -0000 Date: Thu, 23 Jan 2020 22:27:26 -0500 From: Rich Felker To: musl@lists.openwall.com Message-ID: <20200124032726.GQ30412@brightrain.aerifal.cx> References: <20200123041812.GL30412@brightrain.aerifal.cx> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) Sender: Rich Felker Subject: Re: [musl] arm __a_barrier_v6 register value should be zero? On Thu, Jan 23, 2020 at 06:09:57PM -0800, Andre McCurdy wrote: > On Wed, Jan 22, 2020 at 8:18 PM Rich Felker wrote: > > On Wed, Jan 22, 2020 at 05:30:53PM -0800, Andre McCurdy wrote: > > > The arm1176jzfs documentation describing the armv6 CP15 Data Memory > > > Barrier operation seems to specify the register value written to the > > > coprocessor as "SBZ" ie Should Be Zero. See page 216 of: > > > > > > http://infocenter.arm.com/help/topic/com.arm.doc.ddi0301h/DDI0301H_arm1176jzfs_r0p7_trm.pdf > > > > > > However the __a_barrier_v6() function which implements this in musl > > > uses r0 as the register written to the coprocessor and doesn't > > > initialise it. Should __a_barrier_v6() set r0 to 0 before issuing the > > > mcr instruction? Or is it defined somewhere that this register value > > > doesn't matter? > > > > __a_barrier_* have a contract not to clobber r0 -- see the calling > > code in arch/arm/atomic_arch.h: > > > > static inline void a_barrier() > > { > > register uintptr_t ip __asm__("ip") = __a_barrier_ptr; > > __asm__ __volatile__( BLX " ip" : "+r"(ip) : : "memory", "cc", "lr" ); > > } > > > > We could probably switch to using ip as the register if needed. > > However looking at Linux kernel source, no effort is made to zero the > > register used (see arch/arm/include/asm/assembler.h for the definition > > of the smp_dmb macro) so I think it must not actually matter... > > > > Nice find, though. Let's see if we can get a better authoritative > > answer on it. > > OK. Another question: what's the reason for testing that the 3rd char > of AT_PLATFORM isn't [0-9] in __set_thread_area()? Isn't just testing > that the first two chars are "v6" enough to confirm armv6? Indeed I suppose we should test that, though I don't seem "armv60" as being likely now that they've mostly moved on to 64-bit for new isa levels... Rich