From: Rich Felker <dalias@libc.org>
To: musl@lists.openwall.com
Subject: Re: [musl] 答复: [musl] musl support riscv32
Date: Thu, 12 Mar 2020 22:13:18 -0400 [thread overview]
Message-ID: <20200313021318.GL11469@brightrain.aerifal.cx> (raw)
In-Reply-To: <7D9266CBFB4E9A4B9C7B1D0341567D8601728046@DGGEMI529-MBX.china.huawei.com>
On Fri, Mar 13, 2020 at 02:05:09AM +0000, chengzhiwei (C) wrote:
> Thanks, Hopefully I am!
>
> Another thing is about atomic operation(if 32-bit based on what's
> upstram in musl for riscv64), musl's atomic operation for riscv64 is
> a handwritten assembly version, but some RISCV-V MCU omit such
> instructions LR/SC specified in the A standard extension. Someone do
> related work to support processors without atomic instructions? Or
> considering the possibility of implementing the functionality in C
> code.
If the hardware lacks them the kernel needs to trap and emulate, or
provide some other mechanism (like kuser_helper on old ARM). There's
no way to have a working implementation without compare-and-swap.
I've said many times that it's ridiculous that RISC-V made them
optional. For a single-core CPU LR/SC are trivial to implement. LR
just sets a flag and all interrupts clear the flag. SC stores only if
the flag is set.
Rich
next prev parent reply other threads:[~2020-03-13 2:13 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-12 11:09 chengzhiwei (C)
2020-03-12 13:57 ` Rich Felker
2020-03-13 2:05 ` [musl] 答复: " chengzhiwei (C)
2020-03-13 2:13 ` Rich Felker [this message]
[not found] ` <202003130543.02D5h9Zk085624@ATCSQR.andestech.com>
2020-03-13 6:02 ` Ruinland ChuanTzu Tsai
2020-03-13 14:05 ` Rich Felker
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