From mboxrd@z Thu Jan 1 00:00:00 1970 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on inbox.vuxu.org X-Spam-Level: X-Spam-Status: No, score=-3.3 required=5.0 tests=MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL autolearn=ham autolearn_force=no version=3.4.4 Received: (qmail 17520 invoked from network); 4 Jun 2020 23:42:56 -0000 Received: from mother.openwall.net (195.42.179.200) by inbox.vuxu.org with ESMTPUTF8; 4 Jun 2020 23:42:56 -0000 Received: (qmail 15833 invoked by uid 550); 4 Jun 2020 23:42:52 -0000 Mailing-List: contact musl-help@lists.openwall.com; run by ezmlm Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-ID: Reply-To: musl@lists.openwall.com Received: (qmail 15815 invoked from network); 4 Jun 2020 23:42:51 -0000 X-Authentication-Warning: gate.crashing.org: segher set sender to segher@kernel.crashing.org using -f Date: Thu, 4 Jun 2020 18:42:35 -0500 From: Segher Boessenkool To: Joseph Myers Cc: Daniel Kolesa , musl@lists.openwall.com, Rich Felker , Michal =?iso-8859-1?Q?Such=E1nek?= , libc-alpha@sourceware.org, eery@paperfox.es, Will Springer , Palmer Dabbelt via binutils , via libc-dev , linuxppc-dev@lists.ozlabs.org Message-ID: <20200604234234.GN31009@gate.crashing.org> References: <20200602142337.GS25173@kitsune.suse.cz> <3aeb6dfe-ae23-42f9-ac23-16be6b54a850@www.fastmail.com> <20200604171232.GG31009@gate.crashing.org> <20200604171844.GO1079@brightrain.aerifal.cx> <20200604173312.GI31009@gate.crashing.org> <20200604211009.GK31009@gate.crashing.org> <60fa8bd7-2439-4403-a0eb-166a2fb49a4b@www.fastmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.4.2.3i Subject: Re: [musl] Re: ppc64le and 32-bit LE userland compatibility Hi! On Thu, Jun 04, 2020 at 10:08:02PM +0000, Joseph Myers wrote: > > The ELFv2 document specifies things like passing of quadruple precision > > floats. Indeed, VSX is needed there, but that's not a concern if you > > *don't* use quadruple precision floats. > > My understanding is that the registers used for argument passing are all > ones that exactly correspond to the Vector registers in earlier > instruction set versions. In other words, you could *in principle* > produce an object, or a whole libm shared library, [...] And then there is the VRSAVE register, if your OS still uses that. Let's hope not :-) This is similar to what -mno-float128-hardware does (which actually requires VSX hardware for the emulation library currently). Segher