From mboxrd@z Thu Jan 1 00:00:00 1970 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on inbox.vuxu.org X-Spam-Level: X-Spam-Status: No, score=-3.1 required=5.0 tests=DKIM_ADSP_CUSTOM_MED, DKIM_INVALID,DKIM_SIGNED,FREEMAIL_FROM,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL autolearn=ham autolearn_force=no version=3.4.4 Received: (qmail 23428 invoked from network); 11 Jun 2020 08:12:36 -0000 Received: from mother.openwall.net (195.42.179.200) by inbox.vuxu.org with ESMTPUTF8; 11 Jun 2020 08:12:36 -0000 Received: (qmail 30246 invoked by uid 550); 11 Jun 2020 08:12:32 -0000 Mailing-List: contact musl-help@lists.openwall.com; run by ezmlm Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-ID: Reply-To: musl@lists.openwall.com Received: (qmail 30169 invoked from network); 11 Jun 2020 08:12:32 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BzbzYQlqTcjq/Z54VA5i0Fc++eCI+FzbgD9c7ww6d1Y=; b=NO1lPPu9si97eriO3CEk6BJvVIzLod+4jP8SwlnQ/+S1AvLzgMA/M39Y/MdRwgXzMx EN66CvT6OgdHmVHndUmEffKpvKiOGrYngmZybRYdaZijNxeKXNEs1htbYZdc5ZVofpV9 yJBD+sgpvnRfFo4+B7ldbG3mmyPLItf8kxueFFUGggID365ETPXLKlRESRJfpvT6AzLP Gs7/FRIKlaxG5eQOYqqIrKFDK6UR4He2PjfxuVgvc/3CAHtCxnEks5bWadjoGqFUYqiH ejJJvp91B3YKSAkSNVR/OD5cF82+e8jHyMmrDzcFJku10pR20Ya74ZPQovLF5WRrDAEE Esfw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BzbzYQlqTcjq/Z54VA5i0Fc++eCI+FzbgD9c7ww6d1Y=; b=oUqB9bpGXWdNCv5T07BNWZ88qlsxBEI8P3JFN6f7FAjjOczRTHmSrQkPixDqqI1uIS EH+dKQii8VzfxO5D1LplNQZrz7W7fOlL0AfRUdB9HGtKIzzxHZq8s384HaX7vq2/QDFV ABRuY9m1WtB1SrrBfrwjKpoqwkrFd4u+yIpvpI2uo6UaDkpaC+cUvx/gj0cg5gV/h7hH lzYhKFMkCjlpZ7xgRw84UuqnjLsogtUoZ+jclfImntWGNq+6rTVri3rHS20uE+3QOwYw 1UbGpDZdQ6o8KfGdEk1zjiSEOqKWiEhwmnyHasGxrmp6n2QvGUUdpQIFxBSzADT4ja4T Lncg== X-Gm-Message-State: AOAM530dkw6OqPJaiL3ui4WIk4ELe+JDOnNFEmwu6iVBfrXX+nww1yJ4 bBf6swbN22kT/PUx0IpwOIc= X-Google-Smtp-Source: ABdhPJzgTo5usegOpe/iVSOA7fm0pSEeo2rTUxOf7vOJjB1ErBF9OdbQWSt16LmfBhq9t1XurwBUTg== X-Received: by 2002:a5d:6550:: with SMTP id z16mr8738316wrv.392.1591863140736; Thu, 11 Jun 2020 01:12:20 -0700 (PDT) From: Nicholas Piggin To: linuxppc-dev@lists.ozlabs.org Cc: Nicholas Piggin , musl@lists.openwall.com, libc-dev@lists.llvm.org, linux-api@vger.kernel.org Date: Thu, 11 Jun 2020 18:12:02 +1000 Message-Id: <20200611081203.995112-2-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200611081203.995112-1-npiggin@gmail.com> References: <20200611081203.995112-1-npiggin@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [musl] [PATCH 1/2] powerpc/64s/exception: treat NIA below __end_interrupts as soft-masked The scv instruction causes an interrupt which can enter the kernel with MSR[EE]=1, thus allowing interrupts to hit at any time. These must not be taken as normal interrupts, because they come from MSR[PR]=0 context, and yet the kernel stack is not yet set up and r13 is not set to the PACA). Treat this as a soft-masked interrupt regardless of the soft masked state. This does not affect behaviour yet, because currently all interrupts are taken with MSR[EE]=0. Signed-off-by: Nicholas Piggin --- arch/powerpc/kernel/exceptions-64s.S | 27 ++++++++++++++++++++++++--- 1 file changed, 24 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S index e70ebb5c318c..388e34665b4a 100644 --- a/arch/powerpc/kernel/exceptions-64s.S +++ b/arch/powerpc/kernel/exceptions-64s.S @@ -508,8 +508,24 @@ DEFINE_FIXED_SYMBOL(\name\()_common_real) .macro __GEN_COMMON_BODY name .if IMASK + .if ! ISTACK + .error "No support for masked interrupt to use custom stack" + .endif + + /* If coming from user, skip soft-mask tests. */ + andi. r10,r12,MSR_PR + bne 2f + + /* Kernel code running below __end_interrupts is implicitly + * soft-masked */ + LOAD_HANDLER(r10, __end_interrupts) + cmpld r11,r10 + li r10,IMASK + blt- 1f + + /* Test the soft mask state against our interrupt's bit */ lbz r10,PACAIRQSOFTMASK(r13) - andi. r10,r10,IMASK +1: andi. r10,r10,IMASK /* Associate vector numbers with bits in paca->irq_happened */ .if IVEC == 0x500 || IVEC == 0xea0 li r10,PACA_IRQ_EE @@ -540,7 +556,7 @@ DEFINE_FIXED_SYMBOL(\name\()_common_real) .if ISTACK andi. r10,r12,MSR_PR /* See if coming from user */ - mr r10,r1 /* Save r1 */ +2: mr r10,r1 /* Save r1 */ subi r1,r1,INT_FRAME_SIZE /* alloc frame on kernel stack */ beq- 100f ld r1,PACAKSAVE(r13) /* kernel stack to use */ @@ -2838,7 +2854,8 @@ masked_interrupt: ld r10,PACA_EXGEN+EX_R10(r13) ld r11,PACA_EXGEN+EX_R11(r13) ld r12,PACA_EXGEN+EX_R12(r13) - /* returns to kernel where r13 must be set up, so don't restore it */ + ld r13,PACA_EXGEN+EX_R13(r13) + /* May return to masked low address where r13 is not set up */ .if \hsrr HRFI_TO_KERNEL .else @@ -2997,6 +3014,10 @@ EXC_COMMON_BEGIN(ppc64_runlatch_on_trampoline) USE_FIXED_SECTION(virt_trampolines) /* + * All code below __end_interrupts is treated as soft-masked. If + * any code runs here with MSR[EE]=1, it must then cope with pending + * soft interrupt being raised (i.e., by ensuring it is replayed). + * * The __end_interrupts marker must be past the out-of-line (OOL) * handlers, so that they are copied to real address 0x100 when running * a relocatable kernel. This ensures they can be reached from the short -- 2.23.0