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* [musl] Support for PowerPC64 devices lacking AltiVec extentions
@ 2020-08-07 10:15 Gamble, Bradley
  2020-08-07 10:46 ` Szabolcs Nagy
  0 siblings, 1 reply; 3+ messages in thread
From: Gamble, Bradley @ 2020-08-07 10:15 UTC (permalink / raw)
  To: musl


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Hello,


musl currently lists "powerpc64" on it's supported target architectures page. I have been trying to use musl on a device that uses Freescale's T1022/T1042 processors based on the e5500 core - These devices lacks the AltiVec extentions that most other PowerPC64 processors support.

I was initially encountering exceptions with longjmp()/setjmp() due to the use of lvx/stvx instructions to store and restore vector registers. These vector registers are AltiVec-specific and are not required for devices that do not have the AltiVec extentions, so simply removing them was enough to allow musl to function properly on e5500 devices.

I initially considered whether a compile-time check in the configure script was possible, however I believe this has to be a run-time check to query whether the processor supports AltiVec extentions and to conditionally store/restore the registers if it does. I see that Arm targets use __hwcap for platform-specific functionality, and in hwcap.h for PowerPC64 there is a "PPC_FEATURE_HAS_ALTIVEC" definition.

Would this be the correct way to detect this platform-specific behavior?


Kind regards,

bdg

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From 5f1cbe0e73f1fe229494bdf1a8cadc953bb30a06 Mon Sep 17 00:00:00 2001
From: Bradley Gamble <Bradley.Gamble@NCIPHER.COM>
Date: Mon, 3 Aug 2020 13:16:20 +0100
Subject: [PATCH] Remove AltiVec-specific instructions on PowerPC64
 platform. These instructions are used to store and restore the vector
 registers in the setjmp() and longjmp() functions. It was assumed that most
 devices that use the Power ISA also support the AltiVec instruction set,
 however the E5500 core does not support AltiVec and would panic when
 encountering these instructions. Both the instructions and the registers are
 AltiVec-specific, and therefore are not required on non-AltiVec platforms.

---
 src/setjmp/powerpc64/longjmp.s | 15 ---------------
 src/setjmp/powerpc64/setjmp.s  | 15 ---------------
 2 files changed, 30 deletions(-)

diff --git a/src/setjmp/powerpc64/longjmp.s b/src/setjmp/powerpc64/longjmp.s
index 81d45ff6..b4621c63 100644
--- a/src/setjmp/powerpc64/longjmp.s
+++ b/src/setjmp/powerpc64/longjmp.s
@@ -56,21 +56,6 @@ longjmp:
 	lfd 30, 38*8(3)
 	lfd 31, 39*8(3)
 
-	# 6) restore vector registers v20-v31
-	addi 3, 3, 40*8
-	lvx 20, 0, 3 ; addi 3, 3, 16
-	lvx 21, 0, 3 ; addi 3, 3, 16
-	lvx 22, 0, 3 ; addi 3, 3, 16
-	lvx 23, 0, 3 ; addi 3, 3, 16
-	lvx 24, 0, 3 ; addi 3, 3, 16
-	lvx 25, 0, 3 ; addi 3, 3, 16
-	lvx 26, 0, 3 ; addi 3, 3, 16
-	lvx 27, 0, 3 ; addi 3, 3, 16
-	lvx 28, 0, 3 ; addi 3, 3, 16
-	lvx 29, 0, 3 ; addi 3, 3, 16
-	lvx 30, 0, 3 ; addi 3, 3, 16
-	lvx 31, 0, 3
-
 	# 7) return r4 ? r4 : 1
 	mr    3,   4
 	cmpwi cr7, 4, 0
diff --git a/src/setjmp/powerpc64/setjmp.s b/src/setjmp/powerpc64/setjmp.s
index 37683fda..c3f9e37d 100644
--- a/src/setjmp/powerpc64/setjmp.s
+++ b/src/setjmp/powerpc64/setjmp.s
@@ -69,21 +69,6 @@ __setjmp_toc:
 	stfd 30, 38*8(3)
 	stfd 31, 39*8(3)
 
-	# 5) store vector registers v20-v31
-	addi  3, 3, 40*8
-	stvx 20, 0, 3 ; addi 3, 3, 16
-	stvx 21, 0, 3 ; addi 3, 3, 16
-	stvx 22, 0, 3 ; addi 3, 3, 16
-	stvx 23, 0, 3 ; addi 3, 3, 16
-	stvx 24, 0, 3 ; addi 3, 3, 16
-	stvx 25, 0, 3 ; addi 3, 3, 16
-	stvx 26, 0, 3 ; addi 3, 3, 16
-	stvx 27, 0, 3 ; addi 3, 3, 16
-	stvx 28, 0, 3 ; addi 3, 3, 16
-	stvx 29, 0, 3 ; addi 3, 3, 16
-	stvx 30, 0, 3 ; addi 3, 3, 16
-	stvx 31, 0, 3
-
 	# 6) return 0
 	li 3, 0
 	blr
-- 
2.20.1


^ permalink raw reply	[flat|nested] 3+ messages in thread

end of thread, other threads:[~2020-08-07 15:22 UTC | newest]

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2020-08-07 10:15 [musl] Support for PowerPC64 devices lacking AltiVec extentions Gamble, Bradley
2020-08-07 10:46 ` Szabolcs Nagy
2020-08-07 15:22   ` Rich Felker

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