From: 'Rich Felker' <dalias@libc.org>
To: sidneym@codeaurora.org
Cc: musl@lists.openwall.com
Subject: Re: [musl] Hexagon DSP support
Date: Sun, 20 Sep 2020 13:17:08 -0400 [thread overview]
Message-ID: <20200920171707.GC3265@brightrain.aerifal.cx> (raw)
In-Reply-To: <025a01d68f4f$bd211aa0$37634fe0$@codeaurora.org>
On Sun, Sep 20, 2020 at 08:12:47AM -0500, sidneym@codeaurora.org wrote:
> > > > > [...]
> > > > > +#define a_barrier a_barrier
> > > > > +static inline void a_barrier()
> > > > > +{
> > > > > + __asm__ __volatile__ ("barrier" ::: "memory"); }
> > > >
> > > > Is the barrier implied in memw_locked? If not, there need to be
> > > > explicit barriers in all the atomic functions.
> > >
> > > Yes, if there is any memory access on the reserved address the
> > > reservation is lost and the predicate is false.
> >
> > That's not what a barrier means. The question is whether it orders all
> access
> > to *other* memory, not the address with the reservation on it.
> > In other words, musl's a_*() atomics need to be full seq_cst model
> > operations, not relaxed atomics.
>
> Per our spec:
> "Threads in the Hexagon processor follow a sequentially consistent memory
> model at a packet
> granularity. Threads interleave their memory operations with one another in
> an arbitrary but
> fair manner. This results in a consistent program order that is globally
> observable by all
> threads in the same order."
Can you clarify or provide a reference for what 'packet granularity'
means? If there's actually a full builtin seq_cst order I don't see
what the barrier instruction exists for to begin with.
Rich
next prev parent reply other threads:[~2020-09-20 17:17 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-15 13:19 sidneym
2020-04-15 16:30 ` Rich Felker
2020-04-15 17:50 ` sidneym
2020-04-15 18:06 ` Szabolcs Nagy
2020-04-15 18:22 ` sidneym
2020-04-16 9:36 ` Szabolcs Nagy
2020-04-16 15:34 ` Rich Felker
2020-04-16 16:26 ` sidneym
2020-04-16 16:34 ` 'Rich Felker'
2020-04-15 18:26 ` Rich Felker
2020-04-15 19:12 ` sidneym
2020-04-15 19:29 ` 'Rich Felker'
2020-04-30 22:44 ` sidneym
2020-04-30 23:51 ` Rich Felker
2020-05-05 23:37 ` sidneym
2020-05-06 0:59 ` Rich Felker
2020-06-18 16:37 ` sidneym
2020-06-18 21:42 ` Szabolcs Nagy
2020-06-19 21:58 ` sidneym
2020-06-19 22:46 ` Rich Felker
2020-06-20 0:03 ` [musl] strtok Robert Skopalík
2020-06-20 0:15 ` Rich Felker
2020-06-20 0:36 ` Robert Skopalík
2020-06-20 0:46 ` Robert Skopalík
2020-06-20 1:44 ` Rich Felker
2020-06-20 7:07 ` Patrick Oppenlander
2020-06-20 13:00 ` Robert Skopalík
2020-06-22 0:57 ` Bery Saidi
2020-06-20 2:29 ` [musl] Hexagon DSP support sidneym
2020-06-20 3:20 ` Rich Felker
2020-07-20 21:26 ` sidneym
2020-07-23 21:56 ` Szabolcs Nagy
2020-07-24 17:49 ` sidneym
2020-09-16 20:49 ` sidneym
2020-09-17 1:32 ` 'Rich Felker'
2020-09-17 22:31 ` sidneym
2020-09-18 1:08 ` Rich Felker
2020-09-18 8:10 ` Szabolcs Nagy
2020-09-20 13:12 ` sidneym
2020-09-20 17:17 ` 'Rich Felker' [this message]
2020-09-21 14:09 ` sidneym
2020-04-15 18:55 ` Fangrui Song
2021-03-09 20:25 sidneym
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