From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on inbox.vuxu.org X-Spam-Level: X-Spam-Status: No, score=-3.1 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 Received: from second.openwall.net (second.openwall.net [193.110.157.125]) by inbox.vuxu.org (Postfix) with SMTP id 8757A23146 for ; Mon, 26 Feb 2024 03:16:01 +0100 (CET) Received: (qmail 26497 invoked by uid 550); 26 Feb 2024 02:12:27 -0000 Mailing-List: contact musl-help@lists.openwall.com; run by ezmlm Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-ID: Reply-To: musl@lists.openwall.com Received: (qmail 26465 invoked from network); 26 Feb 2024 02:12:27 -0000 Date: Sun, 25 Feb 2024 21:16:04 -0500 From: Rich Felker To: "Venkata Ramanaiah Nalamothu (QUIC)" Cc: "musl@lists.openwall.com" Message-ID: <20240226021604.GF4163@brightrain.aerifal.cx> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) Subject: Re: [musl] RISC-V 32bit port in MUSL upstream On Wed, Nov 08, 2023 at 03:00:09PM +0000, Venkata Ramanaiah Nalamothu (QUIC) wrote: > Ping. I believe this is actually close to ready-to-merge. I just pushed what I think was the last missing prerequisite patch: https://git.musl-libc.org/cgit/musl/commit/?id=19563e1850808af216b1b84263bb7e83cccce506 If the riscv32 port builds and works cleanly now with no further changes to non-arch-specific code, I think it can be upstreamed now. I'll try to take a look at this in the next couple days. Rich > -----Original Message----- > From: Venkata Ramanaiah Nalamothu (QUIC) > Sent: Thursday, October 5, 2023 8:54 AM > To: musl@lists.openwall.com > Subject: RE: [musl] RISC-V 32bit port in MUSL upstream > > Looks like that has changed and the ABI is being considered stable, otherwise GLIBC upstream wouldn't have accepted the RISC-V 32bit port, which is available since 2021 in GLIBC upstream. > As per [1], > * Support for the RISC-V ISA running on Linux has been expanded to run on 32-bit hardware. This is supported for the following ISA and ABI pairs: > - rv32imac ilp32 > - rv32imafdc ilp32 > - rv32imafdc ilp32d > The 32-bit RISC-V port requires at least Linux 5.4, GCC 7.1 and binutils 2.28. > > Regards, > Ram Nalamothu > > [1] https://sourceware.org/pipermail/libc-alpha/2021-February/122207.html > > P.S: Apologies for the repost, the previous response was confusing because of the incorrect formatting. > > -----Original Message----- > From: Markus Wichmann > Sent: Friday, September 29, 2023 8:13 PM > To: musl@lists.openwall.com > Subject: Re: [musl] RISC-V 32bit port in MUSL upstream > > WARNING: This email originated from outside of Qualcomm. Please be wary of any links or attachments, and do not enable macros. > > Am Thu, Sep 28, 2023 at 04:39:37AM +0000 schrieb Venkata Ramanaiah Nalamothu (QUIC): > > Thank you very much for sharing the patch set/development branch. > > > > Looking at your github tree commit history, it seems the tree is actively maintained. > > May I know what is stopping from pushing these changes into MUSL community version? > > Were there any technical challenges or someone just need to find time to work with the community to get the changes reviewed/merged? > > According to [0], main issue for Rich was that it was not a stable ABI yet back in 2020. Has that changed yet? > > Ciao, > Markus > > [0] https://www.openwall.com/lists/musl/2020/03/12/2