From: "Alex Rønne Petersen" <alex@alexrp.com>
To: musl@lists.openwall.com
Cc: "Alex Rønne Petersen" <alex@alexrp.com>
Subject: [musl] [PATCH] riscv: Fix setjmp assembly when compiling for ilp32f/lp64f.
Date: Sat, 29 Jun 2024 04:04:34 +0200 [thread overview]
Message-ID: <20240629020434.488975-1-alex@alexrp.com> (raw)
To keep things simple, I just changed the instruction mnemonics appropriately,
rather than adding complexity by changing the buffer size/offsets based on ABI.
Signed-off-by: Alex Rønne Petersen <alex@alexrp.com>
---
src/setjmp/riscv32/longjmp.S | 30 ++++++++++++++++++------------
src/setjmp/riscv32/setjmp.S | 30 ++++++++++++++++++------------
src/setjmp/riscv64/longjmp.S | 30 ++++++++++++++++++------------
src/setjmp/riscv64/setjmp.S | 30 ++++++++++++++++++------------
4 files changed, 72 insertions(+), 48 deletions(-)
diff --git a/src/setjmp/riscv32/longjmp.S b/src/setjmp/riscv32/longjmp.S
index f9cb3318..b4e5458d 100644
--- a/src/setjmp/riscv32/longjmp.S
+++ b/src/setjmp/riscv32/longjmp.S
@@ -23,18 +23,24 @@ longjmp:
lw ra, 52(a0)
#ifndef __riscv_float_abi_soft
- fld fs0, 56(a0)
- fld fs1, 64(a0)
- fld fs2, 72(a0)
- fld fs3, 80(a0)
- fld fs4, 88(a0)
- fld fs5, 96(a0)
- fld fs6, 104(a0)
- fld fs7, 112(a0)
- fld fs8, 120(a0)
- fld fs9, 128(a0)
- fld fs10, 136(a0)
- fld fs11, 144(a0)
+#ifdef __riscv_float_abi_double
+#define FLX fld
+#else
+#define FLX flw
+#endif
+
+ FLX fs0, 56(a0)
+ FLX fs1, 64(a0)
+ FLX fs2, 72(a0)
+ FLX fs3, 80(a0)
+ FLX fs4, 88(a0)
+ FLX fs5, 96(a0)
+ FLX fs6, 104(a0)
+ FLX fs7, 112(a0)
+ FLX fs8, 120(a0)
+ FLX fs9, 128(a0)
+ FLX fs10, 136(a0)
+ FLX fs11, 144(a0)
#endif
seqz a0, a1
diff --git a/src/setjmp/riscv32/setjmp.S b/src/setjmp/riscv32/setjmp.S
index 8a75cf55..5a1a41ef 100644
--- a/src/setjmp/riscv32/setjmp.S
+++ b/src/setjmp/riscv32/setjmp.S
@@ -23,18 +23,24 @@ setjmp:
sw ra, 52(a0)
#ifndef __riscv_float_abi_soft
- fsd fs0, 56(a0)
- fsd fs1, 64(a0)
- fsd fs2, 72(a0)
- fsd fs3, 80(a0)
- fsd fs4, 88(a0)
- fsd fs5, 96(a0)
- fsd fs6, 104(a0)
- fsd fs7, 112(a0)
- fsd fs8, 120(a0)
- fsd fs9, 128(a0)
- fsd fs10, 136(a0)
- fsd fs11, 144(a0)
+#ifdef __riscv_float_abi_double
+#define FSX fsd
+#else
+#define FSX fsw
+#endif
+
+ FSX fs0, 56(a0)
+ FSX fs1, 64(a0)
+ FSX fs2, 72(a0)
+ FSX fs3, 80(a0)
+ FSX fs4, 88(a0)
+ FSX fs5, 96(a0)
+ FSX fs6, 104(a0)
+ FSX fs7, 112(a0)
+ FSX fs8, 120(a0)
+ FSX fs9, 128(a0)
+ FSX fs10, 136(a0)
+ FSX fs11, 144(a0)
#endif
li a0, 0
diff --git a/src/setjmp/riscv64/longjmp.S b/src/setjmp/riscv64/longjmp.S
index 41e2d210..982475c7 100644
--- a/src/setjmp/riscv64/longjmp.S
+++ b/src/setjmp/riscv64/longjmp.S
@@ -23,18 +23,24 @@ longjmp:
ld ra, 104(a0)
#ifndef __riscv_float_abi_soft
- fld fs0, 112(a0)
- fld fs1, 120(a0)
- fld fs2, 128(a0)
- fld fs3, 136(a0)
- fld fs4, 144(a0)
- fld fs5, 152(a0)
- fld fs6, 160(a0)
- fld fs7, 168(a0)
- fld fs8, 176(a0)
- fld fs9, 184(a0)
- fld fs10, 192(a0)
- fld fs11, 200(a0)
+#ifdef __riscv_float_abi_double
+#define FLX fld
+#else
+#define FLX flw
+#endif
+
+ FLX fs0, 112(a0)
+ FLX fs1, 120(a0)
+ FLX fs2, 128(a0)
+ FLX fs3, 136(a0)
+ FLX fs4, 144(a0)
+ FLX fs5, 152(a0)
+ FLX fs6, 160(a0)
+ FLX fs7, 168(a0)
+ FLX fs8, 176(a0)
+ FLX fs9, 184(a0)
+ FLX fs10, 192(a0)
+ FLX fs11, 200(a0)
#endif
seqz a0, a1
diff --git a/src/setjmp/riscv64/setjmp.S b/src/setjmp/riscv64/setjmp.S
index 51249672..0795bf7d 100644
--- a/src/setjmp/riscv64/setjmp.S
+++ b/src/setjmp/riscv64/setjmp.S
@@ -23,18 +23,24 @@ setjmp:
sd ra, 104(a0)
#ifndef __riscv_float_abi_soft
- fsd fs0, 112(a0)
- fsd fs1, 120(a0)
- fsd fs2, 128(a0)
- fsd fs3, 136(a0)
- fsd fs4, 144(a0)
- fsd fs5, 152(a0)
- fsd fs6, 160(a0)
- fsd fs7, 168(a0)
- fsd fs8, 176(a0)
- fsd fs9, 184(a0)
- fsd fs10, 192(a0)
- fsd fs11, 200(a0)
+#ifdef __riscv_float_abi_double
+#define FSX fsd
+#else
+#define FSX fsw
+#endif
+
+ FSX fs0, 112(a0)
+ FSX fs1, 120(a0)
+ FSX fs2, 128(a0)
+ FSX fs3, 136(a0)
+ FSX fs4, 144(a0)
+ FSX fs5, 152(a0)
+ FSX fs6, 160(a0)
+ FSX fs7, 168(a0)
+ FSX fs8, 176(a0)
+ FSX fs9, 184(a0)
+ FSX fs10, 192(a0)
+ FSX fs11, 200(a0)
#endif
li a0, 0
--
2.40.1
reply other threads:[~2024-06-29 2:04 UTC|newest]
Thread overview: [no followups] expand[flat|nested] mbox.gz Atom feed
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20240629020434.488975-1-alex@alexrp.com \
--to=alex@alexrp.com \
--cc=musl@lists.openwall.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
Code repositories for project(s) associated with this public inbox
https://git.vuxu.org/mirror/musl/
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).