From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on inbox.vuxu.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=5.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H4,RCVD_IN_MSPIKE_WL autolearn=ham autolearn_force=no version=3.4.4 Received: from second.openwall.net (second.openwall.net [193.110.157.125]) by inbox.vuxu.org (Postfix) with SMTP id AD13E25914 for ; Sat, 29 Jun 2024 04:04:59 +0200 (CEST) Received: (qmail 3710 invoked by uid 550); 29 Jun 2024 02:04:52 -0000 Mailing-List: contact musl-help@lists.openwall.com; run by ezmlm Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-ID: Reply-To: musl@lists.openwall.com Received: (qmail 3672 invoked from network); 29 Jun 2024 02:04:51 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alexrp.com; s=alexrp; t=1719626683; x=1720231483; darn=lists.openwall.com; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=6lIDNk/DQ0vnCfj99p2VKZTNIAevP5JwGrDISWS+MsE=; b=TDodM71aW5mw6Jh3NfuMoWKUxtnJAOWef1mHC6LfOFfr7cN8GauHK7Vn6Yc4FhqjQ/ UNpQbNwIQpKsAZhyWEgMnCCwaVecQV9rCbaD+LEcmTtZLe57ty4IlcqyB37NcQi803A3 OwAVa0my8mKrK+x3BqEM8xNEXEqNdb+QDE46UedTw+UgQ9J2pUj0wZs0NTDzw3flHuGl GHV/GP9ZjmN0Lp8qmnsVzMQJjeAjbkweKE0fiOeKtx6NEbf/OZcFNf2DHCyNkQfIfM9+ IxH60DLcC+DXAZKZieHhMReu0RTV7KRwoq/83WBSiAoMHAUr5lR10/JWEtrXzYq5BaAJ Eutg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1719626683; x=1720231483; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=6lIDNk/DQ0vnCfj99p2VKZTNIAevP5JwGrDISWS+MsE=; b=j7sUG30gmgvPTvpz0v6ICeb9gliR1fZkyQRpK7cKLNWIBKIQUQGRFgWJINsGVW32Fd tWaB4xsWcWfMgFyF7all98rBsWrdFEVHw5sEInGtSKsVEPy8w0RRG/13akgX9xeVB7/Q 2VSJazNbV/eH+ILGA1EBXUtMrndzS/8kRzYg40AOQH9a0/1ozgZbWt3kkOTbUDGzL/z1 wpGtaOKpLjsacw3Uqios8n+WznV/roiyWMSgosSzLDBgHBQWwJUOr2O5n/RM4UzyRnRX Jj8V6lRHwSTeP2xIFr3zo9iszYmsd8VIZiz68ccu8l/yoWU4k9ZdYc3LN96TGiaVtOc2 ihxg== X-Gm-Message-State: AOJu0YxQTKVOa7Z/PqbPPcdP+deoBXohJ1v9pHQXDfF1yGhd2MHoPKR2 t8VsNVlVxFruROmNiEGE03NL6Ivayr2zXBD3Odbhz6FeHNnLOYmF/BYwhaRSWwnD9ppmrWRb6vX fNGe86Y1Hh4piB7ji2xYRy0ySaD+jgNXe6Ht86K+OreF1Wnrh5TomWNns1TgiGIc8+2Z/m7+aEV lGKgqS7+gg4SPDq8nf/igWrMUazVJXy/Y4jNI= X-Google-Smtp-Source: AGHT+IFpyG3L6UizkbEl9ddgnJQ7iAZIBbxmcDAqIhfX29L7NVBxyLvA32aZsBexU1yTs+rJBBzy2Q== X-Received: by 2002:a17:906:6a22:b0:a6e:f7bc:dcab with SMTP id a640c23a62f3a-a7245c64dc3mr1459155466b.65.1719626683458; Fri, 28 Jun 2024 19:04:43 -0700 (PDT) From: =?UTF-8?q?Alex=20R=C3=B8nne=20Petersen?= To: musl@lists.openwall.com Cc: =?UTF-8?q?Alex=20R=C3=B8nne=20Petersen?= Date: Sat, 29 Jun 2024 04:04:34 +0200 Message-Id: <20240629020434.488975-1-alex@alexrp.com> X-Mailer: git-send-email 2.40.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [musl] [PATCH] riscv: Fix setjmp assembly when compiling for ilp32f/lp64f. To keep things simple, I just changed the instruction mnemonics appropriately, rather than adding complexity by changing the buffer size/offsets based on ABI. Signed-off-by: Alex Rønne Petersen --- src/setjmp/riscv32/longjmp.S | 30 ++++++++++++++++++------------ src/setjmp/riscv32/setjmp.S | 30 ++++++++++++++++++------------ src/setjmp/riscv64/longjmp.S | 30 ++++++++++++++++++------------ src/setjmp/riscv64/setjmp.S | 30 ++++++++++++++++++------------ 4 files changed, 72 insertions(+), 48 deletions(-) diff --git a/src/setjmp/riscv32/longjmp.S b/src/setjmp/riscv32/longjmp.S index f9cb3318..b4e5458d 100644 --- a/src/setjmp/riscv32/longjmp.S +++ b/src/setjmp/riscv32/longjmp.S @@ -23,18 +23,24 @@ longjmp: lw ra, 52(a0) #ifndef __riscv_float_abi_soft - fld fs0, 56(a0) - fld fs1, 64(a0) - fld fs2, 72(a0) - fld fs3, 80(a0) - fld fs4, 88(a0) - fld fs5, 96(a0) - fld fs6, 104(a0) - fld fs7, 112(a0) - fld fs8, 120(a0) - fld fs9, 128(a0) - fld fs10, 136(a0) - fld fs11, 144(a0) +#ifdef __riscv_float_abi_double +#define FLX fld +#else +#define FLX flw +#endif + + FLX fs0, 56(a0) + FLX fs1, 64(a0) + FLX fs2, 72(a0) + FLX fs3, 80(a0) + FLX fs4, 88(a0) + FLX fs5, 96(a0) + FLX fs6, 104(a0) + FLX fs7, 112(a0) + FLX fs8, 120(a0) + FLX fs9, 128(a0) + FLX fs10, 136(a0) + FLX fs11, 144(a0) #endif seqz a0, a1 diff --git a/src/setjmp/riscv32/setjmp.S b/src/setjmp/riscv32/setjmp.S index 8a75cf55..5a1a41ef 100644 --- a/src/setjmp/riscv32/setjmp.S +++ b/src/setjmp/riscv32/setjmp.S @@ -23,18 +23,24 @@ setjmp: sw ra, 52(a0) #ifndef __riscv_float_abi_soft - fsd fs0, 56(a0) - fsd fs1, 64(a0) - fsd fs2, 72(a0) - fsd fs3, 80(a0) - fsd fs4, 88(a0) - fsd fs5, 96(a0) - fsd fs6, 104(a0) - fsd fs7, 112(a0) - fsd fs8, 120(a0) - fsd fs9, 128(a0) - fsd fs10, 136(a0) - fsd fs11, 144(a0) +#ifdef __riscv_float_abi_double +#define FSX fsd +#else +#define FSX fsw +#endif + + FSX fs0, 56(a0) + FSX fs1, 64(a0) + FSX fs2, 72(a0) + FSX fs3, 80(a0) + FSX fs4, 88(a0) + FSX fs5, 96(a0) + FSX fs6, 104(a0) + FSX fs7, 112(a0) + FSX fs8, 120(a0) + FSX fs9, 128(a0) + FSX fs10, 136(a0) + FSX fs11, 144(a0) #endif li a0, 0 diff --git a/src/setjmp/riscv64/longjmp.S b/src/setjmp/riscv64/longjmp.S index 41e2d210..982475c7 100644 --- a/src/setjmp/riscv64/longjmp.S +++ b/src/setjmp/riscv64/longjmp.S @@ -23,18 +23,24 @@ longjmp: ld ra, 104(a0) #ifndef __riscv_float_abi_soft - fld fs0, 112(a0) - fld fs1, 120(a0) - fld fs2, 128(a0) - fld fs3, 136(a0) - fld fs4, 144(a0) - fld fs5, 152(a0) - fld fs6, 160(a0) - fld fs7, 168(a0) - fld fs8, 176(a0) - fld fs9, 184(a0) - fld fs10, 192(a0) - fld fs11, 200(a0) +#ifdef __riscv_float_abi_double +#define FLX fld +#else +#define FLX flw +#endif + + FLX fs0, 112(a0) + FLX fs1, 120(a0) + FLX fs2, 128(a0) + FLX fs3, 136(a0) + FLX fs4, 144(a0) + FLX fs5, 152(a0) + FLX fs6, 160(a0) + FLX fs7, 168(a0) + FLX fs8, 176(a0) + FLX fs9, 184(a0) + FLX fs10, 192(a0) + FLX fs11, 200(a0) #endif seqz a0, a1 diff --git a/src/setjmp/riscv64/setjmp.S b/src/setjmp/riscv64/setjmp.S index 51249672..0795bf7d 100644 --- a/src/setjmp/riscv64/setjmp.S +++ b/src/setjmp/riscv64/setjmp.S @@ -23,18 +23,24 @@ setjmp: sd ra, 104(a0) #ifndef __riscv_float_abi_soft - fsd fs0, 112(a0) - fsd fs1, 120(a0) - fsd fs2, 128(a0) - fsd fs3, 136(a0) - fsd fs4, 144(a0) - fsd fs5, 152(a0) - fsd fs6, 160(a0) - fsd fs7, 168(a0) - fsd fs8, 176(a0) - fsd fs9, 184(a0) - fsd fs10, 192(a0) - fsd fs11, 200(a0) +#ifdef __riscv_float_abi_double +#define FSX fsd +#else +#define FSX fsw +#endif + + FSX fs0, 112(a0) + FSX fs1, 120(a0) + FSX fs2, 128(a0) + FSX fs3, 136(a0) + FSX fs4, 144(a0) + FSX fs5, 152(a0) + FSX fs6, 160(a0) + FSX fs7, 168(a0) + FSX fs8, 176(a0) + FSX fs9, 184(a0) + FSX fs10, 192(a0) + FSX fs11, 200(a0) #endif li a0, 0 -- 2.40.1