From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on inbox.vuxu.org X-Spam-Level: X-Spam-Status: No, score=-3.3 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED,RCVD_IN_MSPIKE_H5, RCVD_IN_MSPIKE_WL,RCVD_IN_ZEN_BLOCKED_OPENDNS autolearn=ham autolearn_force=no version=3.4.4 Received: from second.openwall.net (second.openwall.net [193.110.157.125]) by inbox.vuxu.org (Postfix) with SMTP id EBF9D238B8 for ; Thu, 18 Sep 2025 18:47:58 +0200 (CEST) Received: (qmail 17563 invoked by uid 550); 18 Sep 2025 16:47:54 -0000 Mailing-List: contact musl-help@lists.openwall.com; run by ezmlm Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-ID: Reply-To: musl@lists.openwall.com x-ms-reactions: disallow Received: (qmail 17521 invoked from network); 18 Sep 2025 16:47:54 -0000 From: Pincheng Wang To: musl@lists.openwall.com Cc: pincheng.plct@isrc.iscas.ac.cn Date: Fri, 19 Sep 2025 00:47:19 +0800 Message-Id: <20250918164720.337994-1-pincheng.plct@isrc.iscas.ac.cn> X-Mailer: git-send-email 2.39.5 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CM-TRANSID:rQCowADX64WuN8xoKbeTAw--.48055S2 X-Coremail-Antispam: 1UD129KBjvJXoW7Cw1xXF4UXry5uw1UuFy3urg_yoW8WF4rpF W3uw15KFWqgas3C3s3Xws7uw1FqF4Fgw43GF17J34DZ34akFnxKF18Kr1Yya4DJr4xCFy2 9r4UKr18uF1UArDanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUyq14x267AKxVWUJVW8JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26r1j6r1xM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r1j 6r4UM28EF7xvwVC2z280aVAFwI0_Jr0_Gr1l84ACjcxK6I8E87Iv6xkF7I0E14v26r1j6r 4UM2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xII jxv20xvE14v26r1Y6r17McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr 1lF7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7MxAIw28IcxkI7VAKI48J MxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwV AFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUXVWUAwCIc40Y0x0EwIxGrwCI42IY6xIIjxv2 0xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVWUJVW8JwCI42IY6xAIw20EY4 v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aVCY1x0267AK xVWUJVW8JbIYCTnIWIevJa73UjIFyTuYvjfUYDGYDUUUU X-Originating-IP: [120.227.57.35] X-CM-SenderInfo: pslquxhhqjh1xofwqxxvufhxpvfd2hldfou0/ Subject: [musl] [PATCH 0/1] riscv: Add support for Zacas in atomic operations Hi all, This patch adds support for the RISC-V Zacas (Atomic Compare-and-Swap) extension in musl's atomic operations for both riscv64 and riscv32. Currently, musl implements a_cas using a Load-Reserved/Store-Conditional (lr/sc) loop that: - Requires at least four instructions (lr+bne+sc+bnez) per CAS operation, - Contains a retry loop under contention, - Incurs branch penalties that may cause pipeline stalls. Zacas introduces amocas.w.aqrl/amocas.d.aqrl instructions that perform CAS atomically in a single instruction, eliminating retry loops and conditional branches. Due to hardware limitations, we evaluated this change under QEMU using both mcycle and minstret counters. The results show clear benefits: Metric lr/sc Zacas Improvement Instr. per CAS (50k ops average) 15.04 8.36 -44.4% Instr. per op (single-thread) 23.61 14.25 -39.6% Instr. per op (multi-thread, high contention) 528.24 251.14 -52.5% In addition, libc.a size is reduced by ~1.2% due to removal of loop code. The patch automatically falls back to the lr/sc implementation on systems where Zacas is not available, preserving full backward compatibility. This work provides a measurable reduction in instruction count, execution cycles and binary size, improving scalability of synchronization primitives under load. Thanks for reviewing! Best regards, Pincheng Wang Pincheng Wang (1): riscv: add Zacas extension support for atomic CAS arch/riscv32/atomic_arch.h | 17 +++++++++++++++++ arch/riscv64/atomic_arch.h | 30 ++++++++++++++++++++++++++++++ 2 files changed, 47 insertions(+) -- 2.39.5