From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on inbox.vuxu.org X-Spam-Level: X-Spam-Status: No, score=-3.3 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED,RCVD_IN_MSPIKE_H5, RCVD_IN_MSPIKE_WL,RCVD_IN_ZEN_BLOCKED_OPENDNS autolearn=ham autolearn_force=no version=3.4.4 Received: from second.openwall.net (second.openwall.net [193.110.157.125]) by inbox.vuxu.org (Postfix) with SMTP id 211C13152C for ; Thu, 18 Sep 2025 18:48:10 +0200 (CEST) Received: (qmail 17779 invoked by uid 550); 18 Sep 2025 16:47:55 -0000 Mailing-List: contact musl-help@lists.openwall.com; run by ezmlm Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-ID: Reply-To: musl@lists.openwall.com x-ms-reactions: disallow Received: (qmail 17542 invoked from network); 18 Sep 2025 16:47:54 -0000 From: Pincheng Wang To: musl@lists.openwall.com Cc: pincheng.plct@isrc.iscas.ac.cn Date: Fri, 19 Sep 2025 00:47:20 +0800 Message-Id: <20250918164720.337994-2-pincheng.plct@isrc.iscas.ac.cn> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250918164720.337994-1-pincheng.plct@isrc.iscas.ac.cn> References: <20250918164720.337994-1-pincheng.plct@isrc.iscas.ac.cn> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CM-TRANSID:rQCowADX64WuN8xoKbeTAw--.48055S3 X-Coremail-Antispam: 1UD129KBjvJXoW7Zw4ktry5tFWftFy5Gw15Arb_yoW5JrWkpr 4fAwsxCrWUW3s7GrZaqrWDu3W5GFn3GryfJrsFk348ZF1DXr48C3s5GF1jkFyUGa1vvFy0 ka1UGryrWw47X3DanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUU9214x267AKxVWUJVW8JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jr4l82xGYIkIc2 x26xkF7I0E14v26r18M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0Y4vE 2Ix0cI8IcVAFwI0_Jr0_JF4l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Jr0_Gr1l84ACjc xK6I8E87Iv67AKxVWUJVW8JwA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Jr0_Gr1le2I262IY c4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI8IcVAFwI 0_Jrv_JF1lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJVW8JwACjcxG0xvY 0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1l42xK82IYc2Ij64vIr41l4I8I3I0E4I kC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x8GjcxK67AKxVWUGVWU WwC2zVAF1VAY17CE14v26r1Y6r17MIIYrxkI7VAKI48JMIIF0xvE2Ix0cI8IcVAFwI0_Jr 0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26r1j6r4UMIIF0xvE42xK8VAvwI8IcIk0rVWU JVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv6xkF7I0E14v26r1j6r4UYx BIdaVFxhVjvjDU0xZFpf9x0JUk73kUUUUU= X-Originating-IP: [120.227.57.35] X-CM-SenderInfo: pslquxhhqjh1xofwqxxvufhxpvfd2hldfou0/ Subject: [musl] [PATCH 1/1] riscv: add Zacas extension support for atomic CAS Add compile-time detection for RISC-V Zacas extension and use amocas.w.aqrl/amocas.d.aqrl instructions when available. When __riscv_zacas is defined, a_cas() and a_cas_p() use single amocas instructions instead of lr/sc loops. Falls back to existing lr/sc implementation when Zacas is not available. Signed-off-by: Pincheng Wang --- arch/riscv32/atomic_arch.h | 17 +++++++++++++++++ arch/riscv64/atomic_arch.h | 30 ++++++++++++++++++++++++++++++ 2 files changed, 47 insertions(+) diff --git a/arch/riscv32/atomic_arch.h b/arch/riscv32/atomic_arch.h index 4d418f63..64ef05b7 100644 --- a/arch/riscv32/atomic_arch.h +++ b/arch/riscv32/atomic_arch.h @@ -3,6 +3,21 @@ static inline void a_barrier() { __asm__ __volatile__ ("fence rw,rw" : : : "memory"); } +#ifdef __riscv_zacas + +#define a_cas a_cas +static inline int a_cas(volatile int *p, int t, int s) +{ + int old = t; + __asm__ __volatile__ ( + "amocas.w.aqrl %0, %2, %1" + : "+r"(old), "+A"(*(volatile int *)p) + : "r"(s) + : "memory"); + return old; +} + +#else /* Fallback to lr/sc when Zacas is not available */ #define a_cas a_cas static inline int a_cas(volatile int *p, int t, int s) @@ -19,3 +34,5 @@ static inline int a_cas(volatile int *p, int t, int s) : "memory"); return old; } + +#endif /* __riscv_zacas */ \ No newline at end of file diff --git a/arch/riscv64/atomic_arch.h b/arch/riscv64/atomic_arch.h index 0c382588..9681505e 100644 --- a/arch/riscv64/atomic_arch.h +++ b/arch/riscv64/atomic_arch.h @@ -4,6 +4,34 @@ static inline void a_barrier() __asm__ __volatile__ ("fence rw,rw" : : : "memory"); } +#ifdef __riscv_zacas + +#define a_cas a_cas +static inline int a_cas(volatile int *p, int t, int s) +{ + int old = t; + __asm__ __volatile__ ( + "amocas.w.aqrl %0, %2, %1" + : "+r"(old), "+A"(*(volatile int *)p) + : "r"(s) + : "memory"); + return old; +} + +#define a_cas_p a_cas_p +static inline void *a_cas_p(volatile void *p, void *t, void *s) +{ + void *old = t; + __asm__ __volatile__ ( + "amocas.d.aqrl %0, %2, %1" + : "+r"(old), "+A"(*(void *volatile *)p) + : "r"(s) + : "memory"); + return old; +} + +#else /* Fallback to lr/sc when Zacas is not available */ + #define a_cas a_cas static inline int a_cas(volatile int *p, int t, int s) { @@ -36,3 +64,5 @@ static inline void *a_cas_p(volatile void *p, void *t, void *s) : "memory"); return old; } + +#endif /* __riscv_zacas */ -- 2.39.5