Re: [musl] [PATCH 1/1] riscv: add Zacas extension support for atomic CAS

[Szabolcs Nagy <nsz@port70.net>]

* Pincheng Wang <pincheng.plct@isrc.iscas.ac.cn> [2025-09-19 00:47:20 +0800]:
> Add compile-time detection for RISC-V Zacas extension and use
> amocas.w.aqrl/amocas.d.aqrl instructions when available.
> 
> When __riscv_zacas is defined, a_cas() and a_cas_p() use single amocas
> instructions instead of lr/sc loops. Falls back to existing lr/sc
> implementation when Zacas is not available.

is this a supported extension? are there users?
(implemented on existing cpus with released toolchain versions)

what cflags enable the extension? (how to test)

i can't review if the instructions have the right semantics,
but the code looks ok, with some comments below.

> 
> Signed-off-by: Pincheng Wang <pincheng.plct@isrc.iscas.ac.cn>
> ---
>  arch/riscv32/atomic_arch.h | 17 +++++++++++++++++
>  arch/riscv64/atomic_arch.h | 30 ++++++++++++++++++++++++++++++
>  2 files changed, 47 insertions(+)
> 
> diff --git a/arch/riscv32/atomic_arch.h b/arch/riscv32/atomic_arch.h
> index 4d418f63..64ef05b7 100644
> --- a/arch/riscv32/atomic_arch.h
> +++ b/arch/riscv32/atomic_arch.h
>  }
> +#ifdef __riscv_zacas

newline before #ifdef

> +#else /* Fallback to lr/sc when Zacas is not available */
...
> +#endif /* __riscv_zacas */
> \ No newline at end of file

newline after endif

i think ifdef comments are not needed in such a simple file.

> +++ b/arch/riscv64/atomic_arch.h
> @@ -4,6 +4,34 @@ static inline void a_barrier()
>  	__asm__ __volatile__ ("fence rw,rw" : : : "memory");
>  }
>  
> +#ifdef __riscv_zacas
> +
> +#define a_cas a_cas
> +static inline int a_cas(volatile int *p, int t, int s)
> +{
> +	int old = t;
> +	__asm__ __volatile__ (
> +		"amocas.w.aqrl %0, %2, %1"
> +		: "+r"(old), "+A"(*(volatile int *)p)
> +		: "r"(s)
> +		: "memory");

existing cas does not use +A constraint (check git log
why and ensure this is ok).

the ptr cast should not be needed. (same for rv32)