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Date: Fri, 15 Sep 2023 09:45:41 +0200
To: musl@lists.openwall.com
Cc: joao@overdrivepizza.com
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From: =?UTF-8?Q?S=C3=B6ren?= Tempel <soeren@soeren-tempel.net>
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Subject: Re: [musl] Intel CET Support

Hello,

Has there been any progress on this? On the Alpine side of things, there is=

currently an ongoing discussion regarding enabling CET by default, but of c=
ourse
that would presuppose support for this feature in musl [1]. From the Alpine=
 point
of view, support for CET would certainly be interesting!

Maybe it would also be possible to only implement support for
-cf-protection=3Dreturn as a first step? If my understanding of CET is corr=
ect,
doing so would not require adding endbr instructions to assembler files (th=
ese
should only be needed for -cf-protection=3Dbranch). As such, this might mak=
e the
initial diff a bit easier to review?

Greetings
S=C3=B6ren

[1]: https://gitlab.alpinelinux.org/alpine/tsc/-/issues/64

> Hi,
>=20
> Long ago I sent some patches here to enable CET support within MUSL=20
> (https://www.openwall.com/lists/musl/2020/10/19/3).
>=20
> These patches were a result from some experiment I have been running=20
> with clang, and to which I needed a suitable library. I understand that=20=

> the patches were not in their best shape, and I was a bit busy at the=20
> time so I didn't really push this through.
>=20
> Either way, I'm now wondering if there is any interest from MUSL to=20
> support CET. If yes, I can start working on an updated patch-set to be=20=

> sent here eventually.
>=20
> Additionally, if the support is of interest, it would also be=20
> interesting to know if MUSL intends to support CET as specified in the=20=

> X86-64 ABI (where a single linked DSO without the CET bits set disables=20=

> the  feature) or if you have something different in mind.
>=20
> Tks,
> Joao.