Re: build musl for armv7m

["Zhao, Weiming" <weimingz@codeaurora.org>]

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How about using the following test?

!defined(__thumb__) || (__ARM_ARCH_7A__ || __ARM_ARCH_7R__ || __ARM_ARCH 
 > 7)

Because I think those instructions are ISA related, not just arm/thumb. 
For example, using -mcpu=cortex-a8 -mthumb, the original code still 
works.  So if only testing __thumb__, the armv7-a thumb mode will fall 
into the slow path too.


On 6/22/2016 12:19 PM, Rich Felker wrote:
> On Wed, Jun 22, 2016 at 12:08:13PM -0700, Zhao, Weiming wrote:
>> Thanks for reviewing.
>>
>> I add tests for ARMv7m for memcpy.
>>
>> For atomics.s, I think the below are equivalent:
>>
>>       ldr ip,1f  ==> assembler will computes the offset from current inst to the label
>>
>> -    ldr ip,[pc,ip] ==> here the address to be loaded is current PC + ip
>> +    add ip,pc,ip  ==> here, the PC is the same as above
>> +    ldr ip,[ip]
> In the original code, pc reads as the address of the instruction
> following the ".word" mnemonic (2 ARM insns ahead of the current
> instruction). In your version, I believe pc reads as the address of
> the .word (2 thumb insns ahead of the current insn) which would be
> wrong, but I may be wrong; one source I saw suggested that arithmetic
> on pc like this was not even defined in thumb mode on some models.
>
>> But I'm not familiar with the CP15 issue you mentioned.
>> So, anyway, I skip the change for atomics.s in this patch.
> OK. But just know that you can't expect it to work unless that's
> implemented.

>> diff --git a/src/string/arm/memcpy_le.S b/src/string/arm/memcpy_le.S
>> index 4db4844..1137f55 100644
>> --- a/src/string/arm/memcpy_le.S
>> +++ b/src/string/arm/memcpy_le.S
>> @@ -241,7 +241,12 @@ non_congruent:
>>   	beq     2f
>>   	ldr     r5, [r1], #4
>>   	sub     r2, r2, #4
>> +#if (__ARM_ARCH_7A || __ARM_ARCH_7R || __ARM_ARCH > 7)
>>   	orr     r4, r3, r5,             lsl lr
>> +#else
>> +	lsl     r4, r5, lr
>> +	orr     r4, r3, r4
>> +#endif
> These are not the right conditions. The selection should be made based
> on whether the code is being assembled as thumb, not on the ISA
> revision level. As written your patch uses the thumb code on all
> pre-v7 targets.

> Rich

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation


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diff --git a/src/setjmp/arm/longjmp.s b/src/setjmp/arm/longjmp.s
index e28d8f3..e9b9b32 100644
--- a/src/setjmp/arm/longjmp.s
+++ b/src/setjmp/arm/longjmp.s
@@ -8,7 +8,9 @@ longjmp:
 	mov ip,r0
 	movs r0,r1
 	moveq r0,#1
-	ldmia ip!, {v1,v2,v3,v4,v5,v6,sl,fp,sp,lr}
+	ldmia ip!, {v1,v2,v3,v4,v5,v6,sl,fp}
+	ldr sp, [ip]!
+	ldr lr, [ip]!
 
 	adr r1,1f
 	ldr r2,1f
diff --git a/src/setjmp/arm/setjmp.s b/src/setjmp/arm/setjmp.s
index 8779163..fd380b0 100644
--- a/src/setjmp/arm/setjmp.s
+++ b/src/setjmp/arm/setjmp.s
@@ -9,7 +9,9 @@ __setjmp:
 _setjmp:
 setjmp:
 	mov ip,r0
-	stmia ip!,{v1,v2,v3,v4,v5,v6,sl,fp,sp,lr}
+	stmia ip!,{v1,v2,v3,v4,v5,v6,sl,fp}
+	str sp, [ip]!
+	str lr, [ip]!
 	mov r0,#0
 
 	adr r1,1f
diff --git a/src/string/arm/memcpy_le.S b/src/string/arm/memcpy_le.S
index 4db4844..7c61979 100644
--- a/src/string/arm/memcpy_le.S
+++ b/src/string/arm/memcpy_le.S
@@ -241,7 +241,12 @@ non_congruent:
 	beq     2f
 	ldr     r5, [r1], #4
 	sub     r2, r2, #4
+#if !defined(__thumb__) || (__ARM_ARCH_7A__ || __ARM_ARCH_7R__ || __ARM_ARCH > 7)
 	orr     r4, r3, r5,             lsl lr
+#else
+	lsl     r4, r5, lr
+	orr     r4, r3, r4
+#endif
 	mov     r3, r5,                 lsr r12
 	str     r4, [r0], #4
 	cmp     r2, #4
@@ -348,7 +353,12 @@ less_than_thirtytwo:
 
 1:      ldr     r5, [r1], #4
 	sub     r2, r2, #4
+#if !defined(__thumb__) || (__ARM_ARCH_7A__ || __ARM_ARCH_7R__ || __ARM_ARCH > 7)
 	orr     r4, r3, r5,             lsl lr
+#else
+	lsl     r4, r5, lr
+	orr     r4, r3, r4
+#endif
 	mov     r3,     r5,                     lsr r12
 	str     r4, [r0], #4
 	cmp     r2, #4