Re: [musl] [PATCH 1/1] riscv64: optimize memset implementation with vector extension

[Pincheng Wang <pincheng.plct@isrc.iscas.ac.cn>]

On 2025/9/25 23:30, Yao Zi wrote:
> On Thu, Sep 25, 2025 at 09:15:57PM +0800, Pincheng Wang wrote:
>> Use head-tail filling strategy for small sizes and dynamic vsetvli
>> approach for vector loops to reduce branch overhead. Add conditional
>> compilation to fall back to scalar implementation when __riscv_vector is
>> not available.
>>
>> Signed-off-by: Pincheng Wang <pincheng.plct@isrc.iscas.ac.cn>
>> ---
>>   src/string/riscv64/memset.S | 101 ++++++++++++++++++++++++++++++++++++
>>   1 file changed, 101 insertions(+)
>>   create mode 100644 src/string/riscv64/memset.S
>>
>> diff --git a/src/string/riscv64/memset.S b/src/string/riscv64/memset.S
>> new file mode 100644
>> index 00000000..5fc6ee14
>> --- /dev/null
>> +++ b/src/string/riscv64/memset.S
>> @@ -0,0 +1,101 @@
>> +#ifdef __riscv_vector
> 
> I don't think musl is built with V extension specified in march on
> RISC-V platforms by default. Does this patch only benefit builds that
> "-march=rv64gcv" is manually specified in CFLAGS?
> 
> Furthermore, having RVV available at compilation-time doesn't mean it's
> available at runtime. This effectively raises the baseline for RISC-V
> platforms from RV64GC (or even lower) to RV64GCV, where the latter isn't
> implied by the mostly-adapted RVA20 profile.
> 
> Best regards,
> Yao Zi

Hi, Yao

Thank you for your review. This patch currently only takes effect when 
`-march=rv64gcv` is manually specified in CFLAGS. I also understand your 
concern about enabling the vector implementation purely through 
compile-time conditionals.

I am investigating a runtime detection and dispatch mechanism to select 
the appropriate implementation based on actual hardware support. If I 
make progress on this and verify it works as expected, I will update the 
approach in a v2 patch.

Best regards,
Pincheng Wang