From mboxrd@z Thu Jan 1 00:00:00 1970 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on inbox.vuxu.org X-Spam-Level: X-Spam-Status: No, score=-3.1 required=5.0 tests=DKIM_INVALID,DKIM_SIGNED, MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED,RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL autolearn=ham autolearn_force=no version=3.4.4 Received: (qmail 11310 invoked from network); 30 Aug 2023 12:23:50 -0000 Received: from second.openwall.net (193.110.157.125) by inbox.vuxu.org with ESMTPUTF8; 30 Aug 2023 12:23:50 -0000 Received: (qmail 24251 invoked by uid 550); 30 Aug 2023 12:23:14 -0000 Mailing-List: contact musl-help@lists.openwall.com; run by ezmlm Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-ID: Reply-To: musl@lists.openwall.com Received: (qmail 23811 invoked from network); 30 Aug 2023 12:23:09 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=N0W/YlAz44dGtqkbUqWkPXF6pVjSptEqSgSpXatsIFo=; b=EP6dxfGsSG2diLUP5VTyHXC0j+M5gdOaHE854Dm/BYCZcqedT9Si3CvDRuBxIV127GVD 5BVLndK52tl0zHj+GeT3zPRjajEtnd+eVGI/nB4QAclUpMAV4OY14U0E19ehGkbmQnXp MSXwG0rS3zh+y3LFuuYv4fPHcTMi8ZtDxZMpGmo/JqXLFfq9+m5sJUH5FCkExnbI9HQX p+Y5cm4kGaRpSars+o8Ci4kaDfbJH53D3kKBtLAsDPl03NkybfOd9RJbR+BtNzDTG1dh Bfsa77kHVLnIQia/rQHf+re4aNCdtGpL5f2RbbRWRIHuID3WSnWOO8ftasCDrL5TBBNn 1Q== From: Matheus Tavares Bernardino To: CC: Brian Cain , Sid Manning , "Rich Felker" , Fangrui Song , Szabolcs Nagy Date: Wed, 30 Aug 2023 09:22:27 -0300 Message-ID: <4d479701dd2fb1944d2d8d34e0bd8047c5e2d3cb.1693396649.git.quic_mathbern@quicinc.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01b.na.qualcomm.com (10.47.209.197) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: ficg5FHUOZXFnvD9G1KdUblVoRU7y8Gg X-Proofpoint-ORIG-GUID: ficg5FHUOZXFnvD9G1KdUblVoRU7y8Gg X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.601,FMLib:17.11.176.26 definitions=2023-08-29_16,2023-08-29_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=7 clxscore=1015 phishscore=0 spamscore=7 suspectscore=0 bulkscore=0 priorityscore=1501 lowpriorityscore=0 impostorscore=0 malwarescore=0 mlxlogscore=112 adultscore=0 mlxscore=7 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2308100000 definitions=main-2308300115 Subject: [musl] [RFC PATCH 2/5] hexagon: add fenv header and implementation From: Brian Cain --- arch/hexagon/bits/fenv.h | 20 ++++++ src/fenv/hexagon/fenv.S | 144 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 164 insertions(+) create mode 100644 arch/hexagon/bits/fenv.h create mode 100644 src/fenv/hexagon/fenv.S diff --git a/arch/hexagon/bits/fenv.h b/arch/hexagon/bits/fenv.h new file mode 100644 index 00000000..d3349306 --- /dev/null +++ b/arch/hexagon/bits/fenv.h @@ -0,0 +1,20 @@ +#define FE_INVALID (1 << 1) +#define FE_DIVBYZERO (1 << 2) +#define FE_OVERFLOW (1 << 3) +#define FE_UNDERFLOW (1 << 4) +#define FE_INEXACT (1 << 5) +#define FE_ALL_EXCEPT (FE_DIVBYZERO | FE_INEXACT | FE_INVALID | \ + FE_OVERFLOW | FE_UNDERFLOW) + +#define FE_TONEAREST 0x00 +#define FE_TOWARDZERO 0x01 +#define FE_DOWNWARD 0x02 +#define FE_UPWARD 0x03 + +typedef unsigned long fexcept_t; + +typedef struct { + unsigned long __cw; +} fenv_t; + +#define FE_DFL_ENV ((const fenv_t *) -1) diff --git a/src/fenv/hexagon/fenv.S b/src/fenv/hexagon/fenv.S new file mode 100644 index 00000000..f5080a22 --- /dev/null +++ b/src/fenv/hexagon/fenv.S @@ -0,0 +1,144 @@ +/* + * The Hexagon user status register includes five status fields which work + * as sticky flags for the five IEEE-defined exception conditions: + * inexact, overflow, underflow, divide by zero, and invalid. + * A sticky flag is set when the corresponding exception occurs, + * and remains set until explicitly cleared. + * + * usr:23:22 - Rounding Mode + * 00: Round toward nearest + * 01: Round toward zero + * 10: Downward Round toward negative infinity + * 11: Upward Round toward positive infinity + * + * usr:5 - Floating-point IEEE Inexact Sticky Flag. + * usr:4 - Floating-point IEEE Underflow Sticky Flag. + * usr:3 - Floating-point IEEE Overflow Sticky Flag. + * usr:2 - Floating-point IEEE Divide-By-Zero Sticky Flag. + * usr:1 - Floating-point IEEE Invalid Sticky Flag. + * usr:0 - Sticky Saturation Overflow, when 1 saturation occurred. + */ + +#define FE_ALL_EXCEPT 0x3f + +#define USR_FE_MASK 0x3fc0003f +#define RND_MASK (0x3 << 22) +#define RND_NEAR (0x0 << 22) +#define RND_ZERO (0x1 << 22) +#define RND_DOWN (0x2 << 22) +#define RND_UP (0x3 << 22) + +/* + * int feclearexcept(int mask) + */ +.global feclearexcept +.type feclearexcept,@function +feclearexcept: + { + r0 = and(r0, #FE_ALL_EXCEPT) // Only touch the IEEE flag bits. + r1 = usr + } + r1 = and(r1, ~r0) + { + usr = r1 + r0 = #0 + jumpr r31 + } + +/* + * int feraiseexcept(int mask) + */ +.global feraiseexcept +.type feraiseexcept,@function +feraiseexcept: + { + r0 = and(r0, #FE_ALL_EXCEPT) // Only touch the IEEE flag bits. + r1 = usr + } + r1 = or(r1, r0) + { + usr = r1 + r0 = #0 + jumpr r31 + } + + +/* + * int fetestexcept(int mask) + */ +.global fetestexcept +.type fetestexcept,@function +fetestexcept: + { + r0 = and(r0, #FE_ALL_EXCEPT) // Only touch the IEEE flag bits. + r1 = usr + } + { + r0 = and(r1, r0) + jumpr r31 + } + +/* + *int fegetround(void) + */ +.global fegetround +.type fegetround,@function +fegetround: + r0 = usr + r0 = and(r0, ##RND_MASK) + r0 = lsr(r0, #22); + jumpr r31 + +/* + * int __fesetround(int r) + */ +.global __fesetround +.type __fesetround,@function +__fesetround: + { + r0 = and(r0, #0x3) // Can only be 0,1,2, or 3 + r1 = usr + r2 = ##RND_MASK + } + { + r1 = and (r1, ~r2) // Clear the current rounding bits. + r0 = asl (r0, #22) + } + r1 = or(r1, r0) + usr = r1 + { + r0 = #0; jumpr r31 + } + +/* + * int fegetenv(fenv_t *envp) + */ +.global fegetenv +.type fegetenv,@function +fegetenv: + r1 = usr + memw(r0) = r1 + { + r0 = #0 + jumpr r31 + } + +/* + * int fesetenv(const fenv_t *envp) + */ +.global fesetenv +.type fesetenv,@function +fesetenv: + { p0 = cmp.eq(r0, #-1); if (p0.new) r1 = #0 } /* The default mode */ + if (!p0) r1 = memw(r0) /* stored in fenv_t */ + + r2 = ##USR_FE_MASK // USR:FE bit mask + r1 = and(r1, r2) // MASK the input bits with the FE bits + r3 = usr + r3 = and(r3, ~r2) // Clear any currently set FE bits + r3 = or(r3, r1) // Set the newbits + usr = r3 + { + r0 = #0 + jumpr r31 + } -- 2.37.2