[musl] [PATCH v2 0/1] riscv: Add support for Zacas in atomic

[musl] [PATCH v2 0/1] riscv: Add support for Zacas in atomic

[Pincheng Wang]

Hi all,

This patch adds support for the RISC-V Zacas (Atomic Compare-and-Swap)
extension in musl's atomic operations for both riscv64 and riscv32.

Changes from v1:
- Fixed #ifdef formatting; added missing newlines and removed redundant
  comments.
- Changed inline asm constraint from +A to match the earlier CAS
  implementation. The generated assembly is identical, and using r
  instead of +A avoids aliasing an lvalue onto memory.

Currently, musl implements a_cas using a Load-Reserved/Store-Conditional
(lr/sc) loop that:
- Requires at least four instructions (lr+bne+sc+bnez) per CAS
  operation.
- Contains a retry loop under contention.
- Incurs branch penalties that may cause pipeline stalls.

Zacas introduces amocas.w.aqrl/amocas.d.aqrl instructions that perform
CAS atomically in a single instruction, eliminating retry loops and
conditional branches.

Due to hardware limitations, we evaluated this change under QEMU using
both mcycle and minstret counters. The results show clear benefits:

Metric											              lr/sc	    Zacas	  Improvement
Instr. per CAS (50k ops average)				      15.04	    8.36	  -44.4%
Instr. per op (single-thread)					        23.61	    14.25	  -39.6%
Instr. per op (multi-thread, high contention)	528.24	  251.14	-52.5%

The patch automatically falls back to the lr/sc implementation on
systems where Zacas is not available, preserving full backward
compatibility.

The Zacas extension was ratified in November 2023. CPUs such as the
XuanTie C930 already support this extension. The recent RVA23 profile
document also listed Zacas as a development option and states that it
"is intended to become mandatory in the future RVA profile", suggesting
broader adoption.

Thanks,
Pincheng Wang

Pincheng Wang (1):
  riscv: add Zacas extension support for atomic CAS

 arch/riscv32/atomic_arch.h | 18 ++++++++++++++++++
 arch/riscv64/atomic_arch.h | 30 ++++++++++++++++++++++++++++++
 2 files changed, 48 insertions(+)

-- 
2.39.5

[musl] [PATCH v2 1/1] riscv: add Zacas extension support for atomic CAS

[Pincheng Wang]

Add compile-time detection for RISC-V Zacas extension and use
amocas.w.aqrl/amocas.d.aqrl instructions when available.

When __riscv_zacas is defined, a_cas() and a_cas_p() use single amocas
instructions instead of lr/sc loops. Falls back to existing lr/sc
implementation when Zacas is not available.

Signed-off-by: Pincheng Wang <pincheng.plct@isrc.iscas.ac.cn>
---
 arch/riscv32/atomic_arch.h | 18 ++++++++++++++++++
 arch/riscv64/atomic_arch.h | 30 ++++++++++++++++++++++++++++++
 2 files changed, 48 insertions(+)

diff --git a/arch/riscv32/atomic_arch.h b/arch/riscv32/atomic_arch.h
index 4d418f63..a134b780 100644
--- a/arch/riscv32/atomic_arch.h
+++ b/arch/riscv32/atomic_arch.h
@@ -4,6 +4,22 @@ static inline void a_barrier()
 	__asm__ __volatile__ ("fence rw,rw" : : : "memory");
 }
 
+#ifdef __riscv_zacas
+
+#define a_cas a_cas
+static inline int a_cas(volatile int *p, int t, int s)
+{
+	int old = t;
+	__asm__ __volatile__ (
+		"amocas.w.aqrl %0, %2, (%1)"
+		: "+&r"(old)
+		: "r"(p), "r"(s)
+		: "memory");
+	return old;
+}
+
+#else /* Fallback to lr/sc when Zacas is not available */
+
 #define a_cas a_cas
 static inline int a_cas(volatile int *p, int t, int s)
 {
@@ -19,3 +35,5 @@ static inline int a_cas(volatile int *p, int t, int s)
 		: "memory");
 	return old;
 }
+
+#endif
diff --git a/arch/riscv64/atomic_arch.h b/arch/riscv64/atomic_arch.h
index 0c382588..92c47c20 100644
--- a/arch/riscv64/atomic_arch.h
+++ b/arch/riscv64/atomic_arch.h
@@ -4,6 +4,34 @@ static inline void a_barrier()
 	__asm__ __volatile__ ("fence rw,rw" : : : "memory");
 }
 
+#ifdef __riscv_zacas
+
+#define a_cas a_cas
+static inline int a_cas(volatile int *p, int t, int s)
+{
+	int old = t;
+	__asm__ __volatile__ (
+		"amocas.w.aqrl %0, %2, (%1)"
+		: "+&r"(old)
+		: "r"(p), "r"(s)
+		: "memory");
+	return old;
+}
+
+#define a_cas_p a_cas_p
+static inline void *a_cas_p(volatile void *p, void *t, void *s)
+{
+	void *old = t;
+	__asm__ __volatile__ (
+		"amocas.d.aqrl %0, %2, (%1)"
+		: "+&r"(old)
+		: "r"(p), "r"(s)
+		: "memory");
+	return old;
+}
+
+#else /* Fallback to lr/sc when Zacas is not available */
+
 #define a_cas a_cas
 static inline int a_cas(volatile int *p, int t, int s)
 {
@@ -36,3 +64,5 @@ static inline void *a_cas_p(volatile void *p, void *t, void *s)
 		: "memory");
 	return old;
 }
+
+#endif
-- 
2.39.5

[musl] Re: [PATCH v2 0/1] riscv: Add support for Zacas in atomic

[Pincheng Wang]

Hi all,

Just a gentle ping on this patch series. Please let me know if there are 
remaining concerns that I can help address. Happy to update the series 
if needed :)

Thanks,
Pincheng Wang

On 2025/10/31 0:17, Pincheng Wang wrote:
> Hi all,
> 
> This patch adds support for the RISC-V Zacas (Atomic Compare-and-Swap)
> extension in musl's atomic operations for both riscv64 and riscv32.
> 
> Thanks,
> Pincheng Wang
> 
> Pincheng Wang (1):
>    riscv: add Zacas extension support for atomic CAS
> 
>   arch/riscv32/atomic_arch.h | 18 ++++++++++++++++++
>   arch/riscv64/atomic_arch.h | 30 ++++++++++++++++++++++++++++++
>   2 files changed, 48 insertions(+)
>