build musl for armv7m

[weimingz@codeaurora.org]

[-- Attachment #1: Type: text/plain, Size: 385 bytes --]

Hi,

I'm building MUSL with -mcpu=cortex-m3. There are a few .s files that 
cannot be assembled because: (1) use predicated instructions without IT 
instr (2) use sp inside reg list in ldmia/stmia.

Please help to review the attached patch.

Also, is there any easy way of disabling string/arm/memcpy_le.S ? For 
baremetal, unaligned access may be unavailable.

Thanks,
Weiming








[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: 0001-fix-asm-for-cortex-m3.patch --]
[-- Type: text/x-diff; name=0001-fix-asm-for-cortex-m3.patch, Size: 2137 bytes --]

From c8fafd75832b0974be59429c6d59b5c19b535c45 Mon Sep 17 00:00:00 2001
From: Weiming Zhao <weimingz@codeaurora.org>
Date: Tue, 14 Jun 2016 01:36:16 -0700
Subject: [PATCH] fix asm for cortex-m3

---
 src/setjmp/arm/longjmp.s    | 5 ++++-
 src/setjmp/arm/setjmp.s     | 4 +++-
 src/thread/arm/atomics.s    | 3 +++
 src/thread/arm/syscall_cp.s | 1 +
 4 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/src/setjmp/arm/longjmp.s b/src/setjmp/arm/longjmp.s
index e28d8f3..5c85cba 100644
--- a/src/setjmp/arm/longjmp.s
+++ b/src/setjmp/arm/longjmp.s
@@ -7,8 +7,11 @@ _longjmp:
 longjmp:
 	mov ip,r0
 	movs r0,r1
+  it eq
 	moveq r0,#1
-	ldmia ip!, {v1,v2,v3,v4,v5,v6,sl,fp,sp,lr}
+	ldmia ip!, {v1,v2,v3,v4,v5,v6,sl,fp}
+ ldr sp, [ip]!
+ ldr lr, [ip]!
 
 	adr r1,1f
 	ldr r2,1f
diff --git a/src/setjmp/arm/setjmp.s b/src/setjmp/arm/setjmp.s
index 8779163..f13068a 100644
--- a/src/setjmp/arm/setjmp.s
+++ b/src/setjmp/arm/setjmp.s
@@ -9,7 +9,9 @@ __setjmp:
 _setjmp:
 setjmp:
 	mov ip,r0
-	stmia ip!,{v1,v2,v3,v4,v5,v6,sl,fp,sp,lr}
+	stmia ip!,{v1,v2,v3,v4,v5,v6,sl,fp}
+ str sp, [ip]!
+ str lr, [ip]!
 	mov r0,#0
 
 	adr r1,1f
diff --git a/src/thread/arm/atomics.s b/src/thread/arm/atomics.s
index 673fc03..05fd9b9 100644
--- a/src/thread/arm/atomics.s
+++ b/src/thread/arm/atomics.s
@@ -49,6 +49,7 @@ __a_cas_dummy:
 	mov r3,r0
 	ldr r0,[r2]
 	subs r0,r3,r0
+ it eq
 	streq r1,[r2]
 	bx lr
 .global __a_cas_v6
@@ -58,6 +59,7 @@ __a_cas_v6:
 	mcr p15,0,r0,c7,c10,5
 1:	.word 0xe1920f9f        /* ldrex r0,[r2] */
 	subs r0,r3,r0
+ itt eq
 	.word 0x01820f91        /* strexeq r0,r1,[r2] */
 	teqeq r0,#1
 	beq 1b
@@ -70,6 +72,7 @@ __a_cas_v7:
 	.word 0xf57ff05b        /* dmb ish */
 1:	.word 0xe1920f9f        /* ldrex r0,[r2] */
 	subs r0,r3,r0
+ itt eq
 	.word 0x01820f91        /* strexeq r0,r1,[r2] */
 	teqeq r0,#1
 	beq 1b
diff --git a/src/thread/arm/syscall_cp.s b/src/thread/arm/syscall_cp.s
index a5730c0..399700b 100644
--- a/src/thread/arm/syscall_cp.s
+++ b/src/thread/arm/syscall_cp.s
@@ -15,6 +15,7 @@ __syscall_cp_asm:
 __cp_begin:
 	ldr r0,[r0]
 	cmp r0,#0
+ it ne
 	blne __cp_cancel
 	mov r7,r1
 	mov r0,r2
2.8.4