From: Alistair Francis <Alistair.Francis@wdc.com>
To: "musl@lists.openwall.com" <musl@lists.openwall.com>,
"palmer@sifive.com" <palmer@sifive.com>
Subject: Re: [PATCH] correct the operand specifiers in the riscv64 CAS routines
Date: Wed, 25 Sep 2019 23:38:48 +0000 [thread overview]
Message-ID: <9f9fa577ecd95e7de68900a42f7ce88d60112df9.camel@wdc.com> (raw)
In-Reply-To: <20190925033015.9905-1-palmer@sifive.com>
On Tue, 2019-09-24 at 20:30 -0700, Palmer Dabbelt wrote:
> The operand sepcifiers in a_cas and a_casp for riscv64 were
> incorrect:
> there's a backwards branch in the routine, so despite tmp being
> written
> at the end of the assembly fragment it cannot be allocated in one of
> the
> input registers because the input values may be needed for another
> trip
> around the loop.
>
> For code that follows the guarnteed forward progress requirements, he
> backwards branch is rarely taken: SiFive's hardware only fails a
> store
> conditional on execptional cases (ie, instruction cache misses inside
> the loop), and until recently a bug in QEMU allowed back-to-back
> store conditionals to succeed. The bug has been fixed in the latest
> QEMU release, but it turns out that the fix caused this latent bug in
> musl to manifest.
>
> Full disclosure: I haven't actually even compiled musl. I just
> guessed
> this would fix a bug introducted by the new QEMU behavior, Alistair
> (CC'd) actually checked it fixes the problem. The rest is just
> conjecture.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Tested-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> arch/riscv64/atomic_arch.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/riscv64/atomic_arch.h b/arch/riscv64/atomic_arch.h
> index c976534284aa..41ad4d04907c 100644
> --- a/arch/riscv64/atomic_arch.h
> +++ b/arch/riscv64/atomic_arch.h
> @@ -14,7 +14,7 @@ static inline int a_cas(volatile int *p, int t, int
> s)
> " sc.w.aqrl %1, %4, (%2)\n"
> " bnez %1, 1b\n"
> "1:"
> - : "=&r"(old), "=r"(tmp)
> + : "=&r"(old), "=&r"(tmp)
> : "r"(p), "r"(t), "r"(s)
> : "memory");
> return old;
> @@ -31,7 +31,7 @@ static inline void *a_cas_p(volatile void *p, void
> *t, void *s)
> " sc.d.aqrl %1, %4, (%2)\n"
> " bnez %1, 1b\n"
> "1:"
> - : "=&r"(old), "=r"(tmp)
> + : "=&r"(old), "=&r"(tmp)
> : "r"(p), "r"(t), "r"(s)
> : "memory");
> return old;
prev parent reply other threads:[~2019-09-25 23:38 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-25 3:30 Palmer Dabbelt
2019-09-25 6:43 ` Khem Raj
2019-09-25 23:38 ` Alistair Francis [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=9f9fa577ecd95e7de68900a42f7ce88d60112df9.camel@wdc.com \
--to=alistair.francis@wdc.com \
--cc=musl@lists.openwall.com \
--cc=palmer@sifive.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
Code repositories for project(s) associated with this public inbox
https://git.vuxu.org/mirror/musl/
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).