Hi Rich,

The arch/mips/atomic_arch.h uses MIPS2 opcode for LL and SC instructions. Opcodes of these instructions differ on MIPSR6.

Refer to https://github.com/JaydeepIMG/musl-1/tree/fix_atomic_for_MIPS32_R6 for the patch.

From 63428cfc5dfa75d2771ba8205067c438942e1a60 Mon Sep 17 00:00:00 2001
From: Jaydeep Patil <jaydeep.patil@imgtec.com>
Date: Mon, 21 Mar 2016 06:00:39 +0000
Subject: [PATCH] Fix for opcodes of LL/SC instructions for MIPSR6

---
arch/mips/atomic_arch.h | 8 ++++++++
1 file changed, 8 insertions(+)

diff --git a/arch/mips/atomic_arch.h b/arch/mips/atomic_arch.h
index ce2823b..16b1542 100644
--- a/arch/mips/atomic_arch.h
+++ b/arch/mips/atomic_arch.h
@@ -3,9 +3,13 @@ static inline int a_ll(volatile int *p)
{
        int v;
        __asm__ __volatile__ (
+#if __mips_isa_rev < 6
                ".set push ; .set mips2\n\t"
+#endif
                "ll %0, %1"
+#if __mips_isa_rev < 6
                "\n\t.set pop"
+#endif
                : "=r"(v) : "m"(*p));
        return v;
}
@@ -15,9 +19,13 @@ static inline int a_sc(volatile int *p, int v)
{
        int r;
        __asm__ __volatile__ (
+#if __mips_isa_rev < 6
                ".set push ; .set mips2\n\t"
+#endif
                "sc %0, %1"
+#if __mips_isa_rev < 6
                "\n\t.set pop"
+#endif
                : "=r"(r), "=m"(*p) : "0"(v) : "memory");
        return r;
}
--
2.1.4

Regards,
Jaydeep