From mboxrd@z Thu Jan 1 00:00:00 1970 X-Msuck: nntp://news.gmane.org/gmane.linux.lib.musl.general/9715 Path: news.gmane.org!not-for-mail From: Jaydeep Patil Newsgroups: gmane.linux.lib.musl.general Subject: [PATCH] Fix atomic_arch.h for MIPS32 R6 Date: Mon, 21 Mar 2016 06:03:47 +0000 Message-ID: Reply-To: musl@lists.openwall.com NNTP-Posting-Host: plane.gmane.org Mime-Version: 1.0 Content-Type: multipart/alternative; boundary="_000_BD7773622145634B952E5B54ACA8E349AA24AD1CPUMAIL01puimgte_" X-Trace: ger.gmane.org 1458540256 27260 80.91.229.3 (21 Mar 2016 06:04:16 GMT) X-Complaints-To: usenet@ger.gmane.org NNTP-Posting-Date: Mon, 21 Mar 2016 06:04:16 +0000 (UTC) Cc: "musl@lists.openwall.com" , "nsz@port70.net" To: "dalias@libc.org" Original-X-From: musl-return-9728-gllmg-musl=m.gmane.org@lists.openwall.com Mon Mar 21 07:04:16 2016 Return-path: Envelope-to: gllmg-musl@m.gmane.org Original-Received: from mother.openwall.net ([195.42.179.200]) by plane.gmane.org with smtp (Exim 4.69) (envelope-from ) id 1ahswp-00057P-Tj for gllmg-musl@m.gmane.org; Mon, 21 Mar 2016 07:04:16 +0100 Original-Received: (qmail 11578 invoked by uid 550); 21 Mar 2016 06:04:12 -0000 Mailing-List: contact musl-help@lists.openwall.com; run by ezmlm Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-ID: Original-Received: (qmail 11544 invoked from network); 21 Mar 2016 06:04:05 -0000 Thread-Topic: [PATCH] Fix atomic_arch.h for MIPS32 R6 Thread-Index: AdGDNtC/7j6fyhbeSE2bzy1PJLSnqg== Accept-Language: en-IN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [192.168.93.60] Xref: news.gmane.org gmane.linux.lib.musl.general:9715 Archived-At: --_000_BD7773622145634B952E5B54ACA8E349AA24AD1CPUMAIL01puimgte_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi Rich, The arch/mips/atomic_arch.h uses MIPS2 opcode for LL and SC instructions. O= pcodes of these instructions differ on MIPSR6. Refer to https://github.com/JaydeepIMG/musl-1/tree/fix_atomic_for_MIPS32_R6= for the patch. >From 63428cfc5dfa75d2771ba8205067c438942e1a60 Mon Sep 17 00:00:00 2001 From: Jaydeep Patil Date: Mon, 21 Mar 2016 06:00:39 +0000 Subject: [PATCH] Fix for opcodes of LL/SC instructions for MIPSR6 --- arch/mips/atomic_arch.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/mips/atomic_arch.h b/arch/mips/atomic_arch.h index ce2823b..16b1542 100644 --- a/arch/mips/atomic_arch.h +++ b/arch/mips/atomic_arch.h @@ -3,9 +3,13 @@ static inline int a_ll(volatile int *p) { int v; __asm__ __volatile__ ( +#if __mips_isa_rev < 6 ".set push ; .set mips2\n\t" +#endif "ll %0, %1" +#if __mips_isa_rev < 6 "\n\t.set pop" +#endif : "=3Dr"(v) : "m"(*p)); return v; } @@ -15,9 +19,13 @@ static inline int a_sc(volatile int *p, int v) { int r; __asm__ __volatile__ ( +#if __mips_isa_rev < 6 ".set push ; .set mips2\n\t" +#endif "sc %0, %1" +#if __mips_isa_rev < 6 "\n\t.set pop" +#endif : "=3Dr"(r), "=3Dm"(*p) : "0"(v) : "memory"); return r; } -- 2.1.4 Regards, Jaydeep --_000_BD7773622145634B952E5B54ACA8E349AA24AD1CPUMAIL01puimgte_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

Hi Rich,

 

The arch/mips/atomic_arch.h uses MIPS2 opcode for LL= and SC instructions. Opcodes of these instructions differ on MIPSR6.<= /o:p>

 

Refer to https://github.com/JaydeepIMG/musl-1/tree/fix_atomic_for_MIPS32_R6 for = the patch.

 

From 63428cfc5dfa75d2771ba8205067c438942e1a60 Mon Se= p 17 00:00:00 2001

From: Jaydeep Patil <jaydeep.patil@imgtec.com>=

Date: Mon, 21 Mar 2016 06:00:39 +0000=

Subject: [PATCH] Fix for opcodes of LL/SC instructio= ns for MIPSR6

 

---

arch/mips/atomic_arch.h | 8 +++++= ;+++

1 file changed, 8 insertions(+)

 

diff --git a/arch/mips/atomic_arch.h b/arch/mips/ato= mic_arch.h

index ce2823b..16b1542 100644

--- a/arch/mips/atomic_arch.h

+++ b/arch/mips/atomic_arch.h=

@@ -3,9 +3,13 @@ static inline int a_ll(volatile= int *p)

{

        int v;

        __asm__ _= _volatile__ (

+#if __mips_isa_rev < 6

        &nbs= p;       ".set push ; .set mips2\n\t&quo= t;

+#endif

        &nbs= p;       "ll %0, %1"

+#if __mips_isa_rev < 6

        &nbs= p;       "\n\t.set pop"<= /p>

+#endif

        &nbs= p;       : "=3Dr"(v) : "m"= ;(*p));

        return v;=

}

@@ -15,9 +19,13 @@ static inline int a_sc(volati= le int *p, int v)

{

        int r;

        __asm__ _= _volatile__ (

+#if __mips_isa_rev < 6

        &nbs= p;       ".set push ; .set mips2\n\t&quo= t;

+#endif

        &nbs= p;       "sc %0, %1"

+#if __mips_isa_rev < 6

        &nbs= p;       "\n\t.set pop"<= /p>

+#endif

        &nbs= p;       : "=3Dr"(r), "=3Dm&qu= ot;(*p) : "0"(v) : "memory");

        return r;=

}

--

2.1.4

 

Regards,

Jaydeep

 

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