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From: Jaydeep Patil <Jaydeep.Patil@imgtec.com>
To: "musl@lists.openwall.com" <musl@lists.openwall.com>
Cc: "dalias@libc.org" <dalias@libc.org>, "nsz@port70.net" <nsz@port70.net>
Subject: RE: [PATCH] Fix atomic_arch.h for MIPS32 R6
Date: Tue, 22 Mar 2016 04:58:51 +0000	[thread overview]
Message-ID: <BD7773622145634B952E5B54ACA8E349AA24AFEB@PUMAIL01.pu.imgtec.org> (raw)
In-Reply-To: <20160321173754.GC21636@brightrain.aerifal.cx>

>-----Original Message-----
>From: Rich Felker [mailto:dalias@aerifal.cx] On Behalf Of dalias@libc.org
>Sent: 21 March 2016 PM 11:08
>To: musl@lists.openwall.com
>Subject: Re: [musl] [PATCH] Fix atomic_arch.h for MIPS32 R6
>
>On Mon, Mar 21, 2016 at 06:03:47AM +0000, Jaydeep Patil wrote:
>> Hi Rich,
>>
>> The arch/mips/atomic_arch.h uses MIPS2 opcode for LL and SC
>> instructions. Opcodes of these instructions differ on MIPSR6.
>
>Does this mean MIPSR6 is an incompatible ISA that can't run normal MIPS
>binaries? If so that's a messy situation we need to find a way to deal with; if
>the difference is just LLSC though then perhaps the kernel's emulation
>handles it (albeit very slowly).
>
>
>It would be helpful if you could provide a link to the documentation of this
>issue (different opcodes).

Refer to https://imagination-technologies-cloudfront-assets.s3.amazonaws.com/documentation/MD00086-2B-MIPS32BIS-AFP-06.04.pdf (Page 209) for details.

>> Refer to https://github.com/JaydeepIMG/musl-
>1/tree/fix_atomic_for_MIPS32_R6 for the patch.
>>
>> >From 63428cfc5dfa75d2771ba8205067c438942e1a60 Mon Sep 17 00:00:00
>> >2001
>> From: Jaydeep Patil <jaydeep.patil@imgtec.com>
>> Date: Mon, 21 Mar 2016 06:00:39 +0000
>> Subject: [PATCH] Fix for opcodes of LL/SC instructions for MIPSR6
>>
>> ---
>> arch/mips/atomic_arch.h | 8 ++++++++
>> 1 file changed, 8 insertions(+)
>>
>> diff --git a/arch/mips/atomic_arch.h b/arch/mips/atomic_arch.h index
>> ce2823b..16b1542 100644
>> --- a/arch/mips/atomic_arch.h
>> +++ b/arch/mips/atomic_arch.h
>> @@ -3,9 +3,13 @@ static inline int a_ll(volatile int *p) {
>>         int v;
>>         __asm__ __volatile__ (
>> +#if __mips_isa_rev < 6
>>                 ".set push ; .set mips2\n\t"
>> +#endif
>>                 "ll %0, %1"
>> +#if __mips_isa_rev < 6
>>                 "\n\t.set pop"
>> +#endif
>
>I think just the .set mips2 could be inside #ifdef with the push/pop always
>used; that produces less #ifdef clutter. But first we need to figure out the
>above issues.
>

We don't need push/pop if we are not doing mips2

>Rich


  reply	other threads:[~2016-03-22  4:58 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-03-21  6:03 Jaydeep Patil
2016-03-21 17:37 ` dalias
2016-03-22  4:58   ` Jaydeep Patil [this message]
2016-03-22 21:22     ` Rich Felker
2016-03-23  6:37       ` Jaydeep Patil
2016-03-23 15:03         ` Rich Felker
2016-03-28  5:07           ` Jaydeep Patil
2016-03-28 13:04             ` Rich Felker
2016-03-29  2:19               ` Rich Felker
2016-03-29  3:54               ` Jaydeep Patil
2016-03-29  4:10                 ` Rich Felker
2016-03-29  7:16                   ` Jaydeep Patil
2016-03-29 13:32                     ` Rich Felker
2016-03-30  9:45                       ` Jaydeep Patil
2016-03-30 14:29                         ` Rich Felker
2016-03-30 15:28                           ` Rich Felker
2016-03-31  5:20                             ` Jaydeep Patil
2016-03-29  3:55               ` Jaydeep Patil

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