From mboxrd@z Thu Jan 1 00:00:00 1970 X-Msuck: nntp://news.gmane.org/gmane.linux.lib.musl.general/9723 Path: news.gmane.org!not-for-mail From: Jaydeep Patil Newsgroups: gmane.linux.lib.musl.general Subject: RE: [PATCH] Fix atomic_arch.h for MIPS32 R6 Date: Tue, 22 Mar 2016 04:58:51 +0000 Message-ID: References: <20160321173754.GC21636@brightrain.aerifal.cx> Reply-To: musl@lists.openwall.com NNTP-Posting-Host: plane.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable X-Trace: ger.gmane.org 1458622755 21065 80.91.229.3 (22 Mar 2016 04:59:15 GMT) X-Complaints-To: usenet@ger.gmane.org NNTP-Posting-Date: Tue, 22 Mar 2016 04:59:15 +0000 (UTC) Cc: "dalias@libc.org" , "nsz@port70.net" To: "musl@lists.openwall.com" Original-X-From: musl-return-9736-gllmg-musl=m.gmane.org@lists.openwall.com Tue Mar 22 05:59:11 2016 Return-path: Envelope-to: gllmg-musl@m.gmane.org Original-Received: from mother.openwall.net ([195.42.179.200]) by plane.gmane.org with smtp (Exim 4.69) (envelope-from ) id 1aiEPN-0008F3-Un for gllmg-musl@m.gmane.org; Tue, 22 Mar 2016 05:59:10 +0100 Original-Received: (qmail 14013 invoked by uid 550); 22 Mar 2016 04:59:07 -0000 Mailing-List: contact musl-help@lists.openwall.com; run by ezmlm Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-ID: Original-Received: (qmail 13995 invoked from network); 22 Mar 2016 04:59:06 -0000 Thread-Topic: [musl] [PATCH] Fix atomic_arch.h for MIPS32 R6 Thread-Index: AQHRg5hzySIsGLLUbES01dme3Dr6SZ9k53Dg In-Reply-To: <20160321173754.GC21636@brightrain.aerifal.cx> Accept-Language: en-IN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [192.168.93.60] Xref: news.gmane.org gmane.linux.lib.musl.general:9723 Archived-At: >-----Original Message----- >From: Rich Felker [mailto:dalias@aerifal.cx] On Behalf Of dalias@libc.org >Sent: 21 March 2016 PM 11:08 >To: musl@lists.openwall.com >Subject: Re: [musl] [PATCH] Fix atomic_arch.h for MIPS32 R6 > >On Mon, Mar 21, 2016 at 06:03:47AM +0000, Jaydeep Patil wrote: >> Hi Rich, >> >> The arch/mips/atomic_arch.h uses MIPS2 opcode for LL and SC >> instructions. Opcodes of these instructions differ on MIPSR6. > >Does this mean MIPSR6 is an incompatible ISA that can't run normal MIPS >binaries? If so that's a messy situation we need to find a way to deal wit= h; if >the difference is just LLSC though then perhaps the kernel's emulation >handles it (albeit very slowly). > > >It would be helpful if you could provide a link to the documentation of th= is >issue (different opcodes). Refer to https://imagination-technologies-cloudfront-assets.s3.amazonaws.co= m/documentation/MD00086-2B-MIPS32BIS-AFP-06.04.pdf (Page 209) for details. >> Refer to https://github.com/JaydeepIMG/musl- >1/tree/fix_atomic_for_MIPS32_R6 for the patch. >> >> >From 63428cfc5dfa75d2771ba8205067c438942e1a60 Mon Sep 17 00:00:00 >> >2001 >> From: Jaydeep Patil >> Date: Mon, 21 Mar 2016 06:00:39 +0000 >> Subject: [PATCH] Fix for opcodes of LL/SC instructions for MIPSR6 >> >> --- >> arch/mips/atomic_arch.h | 8 ++++++++ >> 1 file changed, 8 insertions(+) >> >> diff --git a/arch/mips/atomic_arch.h b/arch/mips/atomic_arch.h index >> ce2823b..16b1542 100644 >> --- a/arch/mips/atomic_arch.h >> +++ b/arch/mips/atomic_arch.h >> @@ -3,9 +3,13 @@ static inline int a_ll(volatile int *p) { >> int v; >> __asm__ __volatile__ ( >> +#if __mips_isa_rev < 6 >> ".set push ; .set mips2\n\t" >> +#endif >> "ll %0, %1" >> +#if __mips_isa_rev < 6 >> "\n\t.set pop" >> +#endif > >I think just the .set mips2 could be inside #ifdef with the push/pop alway= s >used; that produces less #ifdef clutter. But first we need to figure out t= he >above issues. > We don't need push/pop if we are not doing mips2 >Rich