From mboxrd@z Thu Jan 1 00:00:00 1970 X-Msuck: nntp://news.gmane.org/gmane.linux.lib.musl.general/9724 Path: news.gmane.org!not-for-mail From: Jaydeep Patil Newsgroups: gmane.linux.lib.musl.general Subject: RE: [PATCH] Fix pthread_arch.h for microMIPS Date: Tue, 22 Mar 2016 05:09:39 +0000 Message-ID: References: <20160321174254.GD21636@brightrain.aerifal.cx> Reply-To: musl@lists.openwall.com NNTP-Posting-Host: plane.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable X-Trace: ger.gmane.org 1458623399 29197 80.91.229.3 (22 Mar 2016 05:09:59 GMT) X-Complaints-To: usenet@ger.gmane.org NNTP-Posting-Date: Tue, 22 Mar 2016 05:09:59 +0000 (UTC) Cc: "dalias@libc.org" , "nsz@port70.net" To: "musl@lists.openwall.com" Original-X-From: musl-return-9737-gllmg-musl=m.gmane.org@lists.openwall.com Tue Mar 22 06:09:58 2016 Return-path: Envelope-to: gllmg-musl@m.gmane.org Original-Received: from mother.openwall.net ([195.42.179.200]) by plane.gmane.org with smtp (Exim 4.69) (envelope-from ) id 1aiEZp-00069o-L0 for gllmg-musl@m.gmane.org; Tue, 22 Mar 2016 06:09:57 +0100 Original-Received: (qmail 20401 invoked by uid 550); 22 Mar 2016 05:09:56 -0000 Mailing-List: contact musl-help@lists.openwall.com; run by ezmlm Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-ID: Original-Received: (qmail 20380 invoked from network); 22 Mar 2016 05:09:55 -0000 Thread-Topic: [musl] [PATCH] Fix pthread_arch.h for microMIPS Thread-Index: AdGDV7uQSvPB4JzRRjKIbR2yE1W+LAAE0QiAACNZlUA= In-Reply-To: <20160321174254.GD21636@brightrain.aerifal.cx> Accept-Language: en-IN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [192.168.93.60] Xref: news.gmane.org gmane.linux.lib.musl.general:9724 Archived-At: >-----Original Message----- >From: Rich Felker [mailto:dalias@aerifal.cx] On Behalf Of dalias@libc.org >Sent: 21 March 2016 PM 11:13 >To: musl@lists.openwall.com >Subject: Re: [musl] [PATCH] Fix pthread_arch.h for microMIPS > >On Mon, Mar 21, 2016 at 10:01:02AM +0000, Jaydeep Patil wrote: >> Hi Rich, >> >> The patch fixes a link time error when compiled for microMIPS. The >> pthread_self() function has been modified to use rdhwr instruction >> instead of .word directive. >> The change has been done for both clang and gcc. Functions containing >> .word are not compiled for microMIPS. >> >> Please refer to https://github.com/JaydeepIMG/musl- >1/tree/fix_rdhwr_for_umips for details. >> >> >> >> >From 09e4e395d9f1538edb548ffaa02db74e8e11701e Mon Sep 17 00:00:00 >> >2001 >> From: Jaydeep Patil >> Date: Mon, 21 Mar 2016 09:53:37 +0000 >> Subject: [PATCH] Use rdhwr insn instead of .word for microMIPS >> >> --- >> arch/mips/pthread_arch.h | 10 ++-------- >> arch/mips64/pthread_arch.h | 9 ++------- >> 2 files changed, 4 insertions(+), 15 deletions(-) >> >> diff --git a/arch/mips/pthread_arch.h b/arch/mips/pthread_arch.h index >> 8a49965..30e2394 100644 >> --- a/arch/mips/pthread_arch.h >> +++ b/arch/mips/pthread_arch.h >> @@ -1,13 +1,7 @@ >> static inline struct pthread *__pthread_self() { -#ifdef __clang__ >> - char *tp; >> - __asm__ __volatile__ (".word 0x7c03e83b ; move %0, $3" : "=3Dr" = (tp) : : >"$3" ); >> -#else >> - register char *tp __asm__("$3"); >> - /* rdhwr $3,$29 */ >> - __asm__ __volatile__ (".word 0x7c03e83b" : "=3Dr" (tp) ); >> -#endif >> + register char *tp; >> + __asm__ __volatile__ ("rdhwr %0,$29" : "=3Dr" (tp)); >> return (pthread_t)(tp - 0x7000 - sizeof(struct pthread)); } > >You can't remove the register constraint to use $3 here; the reason for th= e >constraint is not that the opcode is hard-coded, but that the kernel's fas= t-path >emulation for MIPS-I, MIPS-II, and MIPS32r1 cpus that lack support for thi= s >hardware register only works when $3 is used as the destination register. >Otherwise a very slow path for emulation is taken. (On our part, this prob= ably >should be documented in a comment -- sorry it's not.) Yes, $3 must be used > >There are probably other reasons we're using .word instead of the mnemonic >here too; I suspect it fails to assemble without .set to a proper ISA leve= l or >sufficient -march. This needs to be checked. Is there a reason the .word >doesn't work on microMIPS? I thought the 32-bit opcodes were the same but >maybe I'm mistaken. > Assembler fails to compile this function for microMIPS when it sees a .word= .=20 Opcodes also differ for microMIPS.=20 Refer to https://imagination-technologies-cloudfront-assets.s3.amazonaws.co= m/documentation/MD00086-2B-MIPS32BIS-AFP-06.04.pdf (Page 320) for details. >Rich