From mboxrd@z Thu Jan 1 00:00:00 1970 X-Msuck: nntp://news.gmane.org/gmane.linux.lib.musl.general/11218 Path: news.gmane.org!.POSTED!not-for-mail From: Jaydeep Patil Newsgroups: gmane.linux.lib.musl.general Subject: RE: [MUSL] microMIPS32R2 O32 port Date: Fri, 7 Apr 2017 06:47:57 +0000 Message-ID: References: <20170406161804.GM17319@brightrain.aerifal.cx> Reply-To: musl@lists.openwall.com NNTP-Posting-Host: blaine.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable X-Trace: blaine.gmane.org 1491547707 15295 195.159.176.226 (7 Apr 2017 06:48:27 GMT) X-Complaints-To: usenet@blaine.gmane.org NNTP-Posting-Date: Fri, 7 Apr 2017 06:48:27 +0000 (UTC) To: "musl@lists.openwall.com" Original-X-From: musl-return-11233-gllmg-musl=m.gmane.org@lists.openwall.com Fri Apr 07 08:48:22 2017 Return-path: Envelope-to: gllmg-musl@m.gmane.org Original-Received: from mother.openwall.net ([195.42.179.200]) by blaine.gmane.org with smtp (Exim 4.84_2) (envelope-from ) id 1cwNgq-0002cY-OQ for gllmg-musl@m.gmane.org; Fri, 07 Apr 2017 08:48:12 +0200 Original-Received: (qmail 15412 invoked by uid 550); 7 Apr 2017 06:48:15 -0000 Mailing-List: contact musl-help@lists.openwall.com; run by ezmlm Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-ID: Original-Received: (qmail 15394 invoked from network); 7 Apr 2017 06:48:14 -0000 Thread-Topic: [musl] [MUSL] microMIPS32R2 O32 port Thread-Index: AdKt1iVvBw5zYQz8QaWQDACqF692CAA7R8oAACltEkA= In-Reply-To: <20170406161804.GM17319@brightrain.aerifal.cx> Accept-Language: en-IN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [192.168.93.60] Xref: news.gmane.org gmane.linux.lib.musl.general:11218 Archived-At: Hi Rich, microMIPS is an Application Specific Extension (ASE) to MIPS cores. Both mi= croMIPS and MIPS can co-exist. MIPS code can call microMIPS and vice-versa. microMIPS is a compressed ISA and contains both 16 and 32-bit instructions = for code size benefit.=20 microMIPS revision R2 to R5 contains branch instructions with delay slot, h= owever microMIPS revision R6 does not contain delay slots (B changed to BC)= .=20 Assembler converts a B+NOP to BC when assembled for R6. Thus we have remove= d non-NOP instructions from the delay slot so that same code can be used fo= r R6. Regards, Jaydeep >-----Original Message----- >From: Rich Felker [mailto:dalias@aerifal.cx] On Behalf Of dalias@libc.org >Sent: 06 April 2017 PM 09:48 >To: musl@lists.openwall.com >Subject: Re: [musl] [MUSL] microMIPS32R2 O32 port > >On Wed, Apr 05, 2017 at 06:33:01AM +0000, Jaydeep Patil wrote: >> Hi Rich, >> >> Please refer to >> https://github.com/JaydeepIMG/musl-1/tree/micromips32r2_v1 for >> microMIPS32R2 O32 port. I have also attached the patch >> (microMIPS32R2_v1_port.patch) for your reference. >> Could you please review it? > >Some important first questions: > >Is micromips an ISA level or a new ISA? This is the same question as last = time >with MIPS r6 and the answer was not obvious and seemingly intentionally >obscured by the official documentation. The answer is important to how we >approach supporting it. Do cpus that support micromips also support plain >mips? Is it like thumb where arm/thumb code can be linked together and cal= l >into one another in the same process, or are they different modes? > >Once we answer those questions, can you provide justifications for the >proposed changes? From your patches it looks like branch delay slots don't >exist in micromips mode. There may be other differences too; I didn't read= it >in detail. Rather than add a bunch of ifdefs I'd rather figure out how we = can >generalize the code so that it's compatible with both. This is what was do= ne on >arm when making it so the asm can be compiled as thumb2. > >Rich