From mboxrd@z Thu Jan 1 00:00:00 1970 X-Msuck: nntp://news.gmane.org/gmane.linux.lib.musl.general/11239 Path: news.gmane.org!.POSTED!not-for-mail From: Jaydeep Patil Newsgroups: gmane.linux.lib.musl.general Subject: RE: [MUSL] microMIPS32R2 O32 port Date: Thu, 13 Apr 2017 10:37:05 +0000 Message-ID: References: <20170406161804.GM17319@brightrain.aerifal.cx> <20170407141941.GQ17319@brightrain.aerifal.cx> <20170412192535.GG2082@port70.net> <20170412202721.GY17319@brightrain.aerifal.cx> <20170413090036.GH2082@port70.net> Reply-To: musl@lists.openwall.com NNTP-Posting-Host: blaine.gmane.org Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="_002_BD7773622145634B952E5B54ACA8E349DAE2CAB5PUMAIL01puimgte_" X-Trace: blaine.gmane.org 1492079843 16926 195.159.176.226 (13 Apr 2017 10:37:23 GMT) X-Complaints-To: usenet@blaine.gmane.org NNTP-Posting-Date: Thu, 13 Apr 2017 10:37:23 +0000 (UTC) Cc: Andre McCurdy To: Szabolcs Nagy , "musl@lists.openwall.com" Original-X-From: musl-return-11254-gllmg-musl=m.gmane.org@lists.openwall.com Thu Apr 13 12:37:19 2017 Return-path: Envelope-to: gllmg-musl@m.gmane.org Original-Received: from mother.openwall.net ([195.42.179.200]) by blaine.gmane.org with smtp (Exim 4.84_2) (envelope-from ) id 1cyc7r-0004JF-HM for gllmg-musl@m.gmane.org; Thu, 13 Apr 2017 12:37:19 +0200 Original-Received: (qmail 3481 invoked by uid 550); 13 Apr 2017 10:37:22 -0000 Mailing-List: contact musl-help@lists.openwall.com; run by ezmlm Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-ID: Original-Received: (qmail 3459 invoked from network); 13 Apr 2017 10:37:21 -0000 Thread-Topic: [musl] [MUSL] microMIPS32R2 O32 port Thread-Index: AdKt1iVvBw5zYQz8QaWQDACqF692CAA7R8oAACltEkAABLsbgAEB0oLgAARReIAAAig8gAACyxwAABlXkqD///FggP//iRXw In-Reply-To: <20170413090036.GH2082@port70.net> Accept-Language: en-IN, en-US Content-Language: en-US X-MS-Has-Attach: yes X-MS-TNEF-Correlator: x-originating-ip: [192.168.93.60] Xref: news.gmane.org gmane.linux.lib.musl.general:11239 Archived-At: --_002_BD7773622145634B952E5B54ACA8E349DAE2CAB5PUMAIL01puimgte_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi Szabolcs, Please find the attached patch. Thanks, Jaydeep >-----Original Message----- >From: Szabolcs Nagy [mailto:nsz@port70.net] >Sent: 13 April 2017 PM 02:31 >To: musl@lists.openwall.com >Cc: Andre McCurdy; Jaydeep Patil >Subject: Re: [musl] [MUSL] microMIPS32R2 O32 port > >* Jaydeep Patil [2017-04-13 04:29:10 +0000]: >> With this branch (micromips32r2_v2) we are supporting microMIPS cores >that co-exist with MIPS. The MUSL library must be built with -minterlink- >compressed option as there are couple of hand-written MIPS only functions. >For microMIPS only cores we will create a different subarch. >> > >ok the _v2 branch makes sense to me >(the patch is sufficiently small that >you can send it to the list) > >i think i was looking at _v1 before > >> >-----Original Message----- >> >From: Andre McCurdy [mailto:armccurdy@gmail.com] >> >Sent: 13 April 2017 AM 03:17 >> >To: musl@lists.openwall.com >> >Cc: Jaydeep Patil >> >Subject: Re: [musl] [MUSL] microMIPS32R2 O32 port >> > >> >On Wed, Apr 12, 2017 at 1:27 PM, Rich Felker wrote: >> >> On Wed, Apr 12, 2017 at 09:25:35PM +0200, Szabolcs Nagy wrote: >> >>> * Jaydeep Patil [2017-04-12 11:54:10 >+0000]: >> >>> > Hi Rich, >> >>> > >> >>> > We can reuse existing MIPS code for microMIPS. There are places >> >>> > where >> >we read from $ra must be compiled for MIPS. >> >>> > Please refer to https://github.com/JaydeepIMG/musl- >> >1/tree/micromips32r2_v2 for modifications. >> >>> > >> >>> >> >>> is micromips a different encoding for mips instructions that works >> >>> on some cpus but not others? >> >> >> >> Yes, it's something like thumb or thumb2 on arm, or the riscv >> >> compressed isa. What I'm not clear on is whether there are >> >> micromips-only cpu models that can't execute normal mips. >> > >> >According to: >> > >> > https://imagination-technologies-cloudfront- >> >>assets.s3.amazonaws.com/documentation/MIPS_Architecture_microMIPS3 >2 >> >_InstructionSet_AFP_P_MD00582_06.04.pdf >> > >> >"microMIPS is also an alternative to the MIPS(r) instruction encoding >> >and can be implemented in parallel or stand-alone." >> > >> >"If only one ISA mode exists (either MIPS or microMIPS) then this >> >mode switch mechanism does not exist" >> > >> >> If so we probably need the ability to build musl as micromips, but >> >> as long as cpus which support both support interworking (calls >> >> between the two type of code in the same process) reasonably, I >> >> don't think there's any reason to consider it a different subarch. >> >> >> >> If not (that is, if all cpus that support micromips also support >> >> the normal mips isa) then I fail to see why there's any need to >> >> compile musl's asm files as micromips. They're not size or >> >> performance bottlenecks. >> >> >> >> Rich --_002_BD7773622145634B952E5B54ACA8E349DAE2CAB5PUMAIL01puimgte_ Content-Type: application/octet-stream; name="microMIPS_32R2_v2.patch" Content-Description: microMIPS_32R2_v2.patch Content-Disposition: attachment; filename="microMIPS_32R2_v2.patch"; size=1468; creation-date="Tue, 04 Apr 2017 07:11:32 GMT"; modification-date="Wed, 12 Apr 2017 10:16:33 GMT" Content-Transfer-Encoding: base64 ZGlmZiAtLWdpdCBhL2FyY2gvbWlwcy9jcnRfYXJjaC5oIGIvYXJjaC9taXBzL2NydF9hcmNoLmgK aW5kZXggOWZjNTBkNy4uNzg4MzJiMCAxMDA2NDQKLS0tIGEvYXJjaC9taXBzL2NydF9hcmNoLmgK KysrIGIvYXJjaC9taXBzL2NydF9hcmNoLmgKQEAgLTEsNiArMSw3IEBACiBfX2FzbV9fKAogIi5z ZXQgcHVzaFxuIgogIi5zZXQgbm9yZW9yZGVyXG4iCisiLnNldCBub21pY3JvbWlwc1xuIgogIi50 ZXh0IFxuIgogIi5nbG9iYWwgXyIgU1RBUlQgIlxuIgogIi5nbG9iYWwgIiBTVEFSVCAiXG4iCmRp ZmYgLS1naXQgYS9hcmNoL21pcHMvcmVsb2MuaCBiL2FyY2gvbWlwcy9yZWxvYy5oCmluZGV4IGIz ZDU5YTQuLjc3MmIzYWEgMTAwNjQ0Ci0tLSBhL2FyY2gvbWlwcy9yZWxvYy5oCisrKyBiL2FyY2gv bWlwcy9yZWxvYy5oCkBAIC0zNiwxNSArMzYsMjMgQEAKICNkZWZpbmUgQ1JUSk1QKHBjLHNwKSBf X2FzbV9fIF9fdm9sYXRpbGVfXyggXAogCSJtb3ZlICRzcCwlMSA7IGpyICUwIiA6IDogInIiKHBj KSwgInIiKHNwKSA6ICJtZW1vcnkiICkKIAorLyoKKyAqIFdoZW4gY29tcGlsZWQgZm9yIG1pY3Jv TUlQUywgLmFsaWduIG1ha2VzIHN1cmUgdGhhdCAuZ3B3b3JkCisgKiBpcyBwbGFjZWQgYXQgd29y ZCBib3VuZGFyeS4gJHJhIG11c3QgcG9pbnQgdG8gZmlyc3QgLmdwd29yZC4KKyAqIElTQSBiaXQg b2YgJHJhIG11c3QgYmUgY2xlYXJlZCBmb3IgbWljcm9NSVBTIGJlZm9yZSB1c2luZyBpdAorICog YXMgYSBiYXNlIGFkZHJlc3MuIEZvciBNSVBTLCBJU0EgYml0IGlzIGFsd2F5cyB6ZXJvLgorKi8K ICNkZWZpbmUgR0VURlVOQ1NZTShmcCwgc3ltLCBnb3QpIF9fYXNtX18gKCBcCiAJIi5oaWRkZW4g IiAjc3ltICJcbiIgXAogCSIuc2V0IHB1c2ggXG4iIFwKIAkiLnNldCBub3Jlb3JkZXIgXG4iIFwK KwkiCS5hbGlnbiAyIFxuIiBcCiAJIgliYWwgMWYgXG4iIFwKIAkiCSBub3AgXG4iIFwKIAkiCS5n cHdvcmQgLiBcbiIgXAogCSIJLmdwd29yZCAiICNzeW0gIiBcbiIgXAotCSIxOglsdyAlMCwgKCRy YSkgXG4iIFwKKwkiMToJaW5zICRyYSwgJDAsIDAsIDEgXG4iIFwKKwkiCWx3ICUwLCAoJHJhKSBc biIgXAogCSIJc3VidSAlMCwgJHJhLCAlMCBcbiIgXAogCSIJbHcgJHJhLCA0KCRyYSkgXG4iIFwK IAkiCWFkZHUgJTAsICUwLCAkcmEgXG4iIFwKZGlmZiAtLWdpdCBhL3NyYy90aHJlYWQvbWlwcy9z eXNjYWxsX2NwLnMgYi9zcmMvdGhyZWFkL21pcHMvc3lzY2FsbF9jcC5zCmluZGV4IGQyODQ2MjYu LjljNWY1NWUgMTAwNjQ0Ci0tLSBhL3NyYy90aHJlYWQvbWlwcy9zeXNjYWxsX2NwLnMKKysrIGIv c3JjL3RocmVhZC9taXBzL3N5c2NhbGxfY3AucwpAQCAtMSw1ICsxLDUgQEAKIC5zZXQgICAgbm9y ZW9yZGVyCi0KKy5zZXQgICAgbm9taWNyb21pcHMKIC5nbG9iYWwgX19jcF9iZWdpbgogLmhpZGRl biBfX2NwX2JlZ2luCiAudHlwZSAgIF9fY3BfYmVnaW4sQGZ1bmN0aW9uCg== --_002_BD7773622145634B952E5B54ACA8E349DAE2CAB5PUMAIL01puimgte_--