From mboxrd@z Thu Jan 1 00:00:00 1970 X-Msuck: nntp://news.gmane.org/gmane.linux.lib.musl.general/11252 Path: news.gmane.org!.POSTED!not-for-mail From: Jaydeep Patil Newsgroups: gmane.linux.lib.musl.general Subject: RE: [MUSL] microMIPS32R2 O32 port Date: Fri, 21 Apr 2017 09:40:45 +0000 Message-ID: References: <20170406161804.GM17319@brightrain.aerifal.cx> <20170407141941.GQ17319@brightrain.aerifal.cx> <20170412192535.GG2082@port70.net> <20170412202721.GY17319@brightrain.aerifal.cx> <20170413090036.GH2082@port70.net> Reply-To: musl@lists.openwall.com NNTP-Posting-Host: blaine.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable X-Trace: blaine.gmane.org 1492767664 9697 195.159.176.226 (21 Apr 2017 09:41:04 GMT) X-Complaints-To: usenet@blaine.gmane.org NNTP-Posting-Date: Fri, 21 Apr 2017 09:41:04 +0000 (UTC) Cc: Andre McCurdy To: "musl@lists.openwall.com" , Szabolcs Nagy Original-X-From: musl-return-11267-gllmg-musl=m.gmane.org@lists.openwall.com Fri Apr 21 11:41:00 2017 Return-path: Envelope-to: gllmg-musl@m.gmane.org Original-Received: from mother.openwall.net ([195.42.179.200]) by blaine.gmane.org with smtp (Exim 4.84_2) (envelope-from ) id 1d1V3i-0002Oy-VL for gllmg-musl@m.gmane.org; Fri, 21 Apr 2017 11:40:59 +0200 Original-Received: (qmail 18173 invoked by uid 550); 21 Apr 2017 09:41:01 -0000 Mailing-List: contact musl-help@lists.openwall.com; run by ezmlm Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-ID: Original-Received: (qmail 18155 invoked from network); 21 Apr 2017 09:41:00 -0000 Thread-Topic: [musl] [MUSL] microMIPS32R2 O32 port Thread-Index: AdKt1iVvBw5zYQz8QaWQDACqF692CAA7R8oAACltEkAABLsbgAEB0oLgAARReIAAAig8gAACyxwAABlXkqD///FggP//iRXw//KPGKA= In-Reply-To: Accept-Language: en-IN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [192.168.93.60] Xref: news.gmane.org gmane.linux.lib.musl.general:11252 Archived-At: Hi Szabolcs, Could you please commit this patch? Thanks, Jaydeep >-----Original Message----- >From: Jaydeep Patil [mailto:Jaydeep.Patil@imgtec.com] >Sent: 13 April 2017 PM 04:07 >To: Szabolcs Nagy; musl@lists.openwall.com >Cc: Andre McCurdy >Subject: RE: [musl] [MUSL] microMIPS32R2 O32 port > >Hi Szabolcs, > >Please find the attached patch. > >Thanks, >Jaydeep > >>-----Original Message----- >>From: Szabolcs Nagy [mailto:nsz@port70.net] >>Sent: 13 April 2017 PM 02:31 >>To: musl@lists.openwall.com >>Cc: Andre McCurdy; Jaydeep Patil >>Subject: Re: [musl] [MUSL] microMIPS32R2 O32 port >> >>* Jaydeep Patil [2017-04-13 04:29:10 +0000]: >>> With this branch (micromips32r2_v2) we are supporting microMIPS cores >>that co-exist with MIPS. The MUSL library must be built with >>-minterlink- compressed option as there are couple of hand-written MIPS >only functions. >>For microMIPS only cores we will create a different subarch. >>> >> >>ok the _v2 branch makes sense to me >>(the patch is sufficiently small that >>you can send it to the list) >> >>i think i was looking at _v1 before >> >>> >-----Original Message----- >>> >From: Andre McCurdy [mailto:armccurdy@gmail.com] >>> >Sent: 13 April 2017 AM 03:17 >>> >To: musl@lists.openwall.com >>> >Cc: Jaydeep Patil >>> >Subject: Re: [musl] [MUSL] microMIPS32R2 O32 port >>> > >>> >On Wed, Apr 12, 2017 at 1:27 PM, Rich Felker wrote: >>> >> On Wed, Apr 12, 2017 at 09:25:35PM +0200, Szabolcs Nagy wrote: >>> >>> * Jaydeep Patil [2017-04-12 11:54:10 >>+0000]: >>> >>> > Hi Rich, >>> >>> > >>> >>> > We can reuse existing MIPS code for microMIPS. There are places >>> >>> > where >>> >we read from $ra must be compiled for MIPS. >>> >>> > Please refer to https://github.com/JaydeepIMG/musl- >>> >1/tree/micromips32r2_v2 for modifications. >>> >>> > >>> >>> >>> >>> is micromips a different encoding for mips instructions that >>> >>> works on some cpus but not others? >>> >> >>> >> Yes, it's something like thumb or thumb2 on arm, or the riscv >>> >> compressed isa. What I'm not clear on is whether there are >>> >> micromips-only cpu models that can't execute normal mips. >>> > >>> >According to: >>> > >>> > https://imagination-technologies-cloudfront- >>> >>>assets.s3.amazonaws.com/documentation/MIPS_Architecture_microMIPS >3 >>2 >>> >_InstructionSet_AFP_P_MD00582_06.04.pdf >>> > >>> >"microMIPS is also an alternative to the MIPS(r) instruction >>> >encoding and can be implemented in parallel or stand-alone." >>> > >>> >"If only one ISA mode exists (either MIPS or microMIPS) then this >>> >mode switch mechanism does not exist" >>> > >>> >> If so we probably need the ability to build musl as micromips, but >>> >> as long as cpus which support both support interworking (calls >>> >> between the two type of code in the same process) reasonably, I >>> >> don't think there's any reason to consider it a different subarch. >>> >> >>> >> If not (that is, if all cpus that support micromips also support >>> >> the normal mips isa) then I fail to see why there's any need to >>> >> compile musl's asm files as micromips. They're not size or >>> >> performance bottlenecks. >>> >> >>> >> Rich