From mboxrd@z Thu Jan 1 00:00:00 1970 X-Msuck: nntp://news.gmane.org/gmane.linux.lib.musl.general/9607 Path: news.gmane.org!not-for-mail From: Masanori Ogino Newsgroups: gmane.linux.lib.musl.general Subject: Re: musl without atomic instructions? Date: Mon, 14 Mar 2016 10:34:22 +0900 Message-ID: References: <20160313002140.GG9349@brightrain.aerifal.cx> Reply-To: musl@lists.openwall.com NNTP-Posting-Host: plane.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 X-Trace: ger.gmane.org 1457919280 12020 80.91.229.3 (14 Mar 2016 01:34:40 GMT) X-Complaints-To: usenet@ger.gmane.org NNTP-Posting-Date: Mon, 14 Mar 2016 01:34:40 +0000 (UTC) To: musl@lists.openwall.com Original-X-From: musl-return-9620-gllmg-musl=m.gmane.org@lists.openwall.com Mon Mar 14 02:34:39 2016 Return-path: Envelope-to: gllmg-musl@m.gmane.org Original-Received: from mother.openwall.net ([195.42.179.200]) by plane.gmane.org with smtp (Exim 4.69) (envelope-from ) id 1afHP5-0001tH-7U for gllmg-musl@m.gmane.org; Mon, 14 Mar 2016 02:34:39 +0100 Original-Received: (qmail 3759 invoked by uid 550); 14 Mar 2016 01:34:35 -0000 Mailing-List: contact musl-help@lists.openwall.com; run by ezmlm Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-ID: Original-Received: (qmail 3737 invoked from network); 14 Mar 2016 01:34:34 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:sender:in-reply-to:references:date:message-id:subject :from:to; bh=nY0UHzCjRX6hJVgO04Y+2gfHGExS+vDBipxHMnDjGB4=; b=A7sfJwtm76I8H791Lq9xl3XgygIUEFTp3R0Znlr9gXRg8H5MG+YowopYxiaCmTeEPa aGet+GuEyisGN4iiVU83Unwmz+rB0mtggiS/Ul0/3C2NAzb2CnECWtbx2r5mt1NRIfca dUJGYNsi0hQKFOc1L0vBanprl/xXRyDJqnvr3/ZpDZfaiL2aZDPzg2hXv9zQT6ybBJbV 8u2xJf/W0ReAsgf6DgFFY7nMek6LA/mAhwn4FepPQHQZLFEKOsg8jJWQ2wZzsaRL+WQI 4g8aOlCcu6dxD4syVRRRte2jNb203E7yOaBXeuhH8pla1+O9GcgIumbGOeOstNkKA05U U5Fg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:sender:in-reply-to:references:date :message-id:subject:from:to; bh=nY0UHzCjRX6hJVgO04Y+2gfHGExS+vDBipxHMnDjGB4=; b=Ovtk025pQFSMidXtnNS7ax1r+8b2FF74DFwnP9P53oe8kpyxUhjEpkc5z07lq1y+Y+ cKGVATBXC3XZXayTYi3pUhO0V8ASdCW8AFtXhfKS3/oOi9UyP47ZgacuFuFX29t78R0F rGET+ne6TKHLLYakk2GOXVUpVWsz2/A+xsz9mKEJha3mHIw4bcoz4Ya1qb9ayarBC07H QAjdFV5N0bHCYtb7Ujoy9ZGlpmfjxL5H3qyXdzZJHfFRhWQC3LXOH/WHOtpm8rcwtp6P HUPhFqBffSi94VoamY3JOnFgkLJVmwhv4DG/pCSieeoXbZxuug1zwhhIFuC2Kc9IEnFZ c9Cg== X-Gm-Message-State: AD7BkJJWAlM1rJNbyNBeg4fGe5Gxl4My5VAWi4ac88Kvm+bK8BsdlZvXam203Tv4yNk65R0yTW0AjEl5rZkVTw== X-Received: by 10.60.150.235 with SMTP id ul11mr11888632oeb.70.1457919262570; Sun, 13 Mar 2016 18:34:22 -0700 (PDT) Original-Sender: masanoriogino@gmail.com In-Reply-To: X-Google-Sender-Auth: HvoFieCCX17ea2DteQDgeeISXeo Xref: news.gmane.org gmane.linux.lib.musl.general:9607 Archived-At: 2016-03-13 9:54 GMT+09:00 Masanori Ogino : > 2016-03-13 9:21 GMT+09:00 Rich Felker : >> Minimal profiles for microcontroller use lack it (this was a >> mistake in the riscv ISA specification, IMO), so if supporting these >> ISA levels is interesting, there are at least three options: >> >> 1. Have the kernel trap the unimplemented instructions and emulate >> them. >> >> 2. Have userspace issue a system call to have the kernel mediate >> atomic accesses. >> >> 3. Integrate atomic sequence restart with the scheduler: at scheduling >> time, the kernel determines if the task being resumed was >> interrupted in the middle of a sequence of instructions that's >> supposed to be atomic, and if so, resets the program counter to the >> beginning of the sequence. (This is how pre-v6 ARM and most SH >> models work.) >> >> Option 3 offers by far the best performance but inherently only works >> on uniprocessor. Options 1 and 2 could theoretically support SMP as >> long as the kernel has some other way of ensuring mutual exclusion and >> memory synchronization between the processors. >> >> Of course the best of all worlds is to have the kernel provide a vdso >> function for atomic cas which it can then provide an optimal >> implementation of for the particular processor being used. Then >> baseline-ISA-level riscv binaries would use the vdso, and ones >> targeting an ISA level that's known to have native atomic instructions >> would use the inline instructions. > > OK, I will ask about the current status on the RISC-V sw-dev ML. On sw-dev, Darius Rad taught me that there is a syscall to perform CAS on RISC-V without the A standard extension. CONFIG_RV_SYSRISCV_ATOMIC enables it (with RISC-V patches.) For reference, the source code is here: https://github.com/riscv/riscv-linux/blob/master/arch/riscv/kernel/sys_riscv.c -- Masanori Ogino