From mboxrd@z Thu Jan 1 00:00:00 1970 X-Msuck: nntp://news.gmane.org/gmane.linux.lib.musl.general/9601 Path: news.gmane.org!not-for-mail From: Masanori Ogino Newsgroups: gmane.linux.lib.musl.general Subject: Re: musl without atomic instructions? Date: Sun, 13 Mar 2016 09:54:58 +0900 Message-ID: References: <20160313002140.GG9349@brightrain.aerifal.cx> Reply-To: musl@lists.openwall.com NNTP-Posting-Host: plane.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 X-Trace: ger.gmane.org 1457830514 12721 80.91.229.3 (13 Mar 2016 00:55:14 GMT) X-Complaints-To: usenet@ger.gmane.org NNTP-Posting-Date: Sun, 13 Mar 2016 00:55:14 +0000 (UTC) To: musl@lists.openwall.com Original-X-From: musl-return-9614-gllmg-musl=m.gmane.org@lists.openwall.com Sun Mar 13 01:55:13 2016 Return-path: Envelope-to: gllmg-musl@m.gmane.org Original-Received: from mother.openwall.net ([195.42.179.200]) by plane.gmane.org with smtp (Exim 4.69) (envelope-from ) id 1aeuJM-0003Ao-Uf for gllmg-musl@m.gmane.org; Sun, 13 Mar 2016 01:55:13 +0100 Original-Received: (qmail 9845 invoked by uid 550); 13 Mar 2016 00:55:10 -0000 Mailing-List: contact musl-help@lists.openwall.com; run by ezmlm Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-ID: Original-Received: (qmail 9826 invoked from network); 13 Mar 2016 00:55:10 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:sender:in-reply-to:references:date:message-id:subject :from:to; bh=U+0PtNcWVZh6Edq5pvLkCDuY+TmQ+DFs0xp51s1VTRI=; b=QlvLIi/gYwYp3+RHLrgGO/09hgNP8d8I26iwFSrj7oyBxGI44Jh+8Lj3jqW9te08Xu wHBapJIvs0dm/Mzr92Zcui1yuAK++fMxi8kshSmUqtZzzQB4gUoxFRFbfR4D0uXISIkD 6aFCdvyErhJEQEh42Ajq/uJSLwkDlUBV2k2r9QEueDXPNHXsnN/B7LEeAhLZdZBQfsV1 TmhcHVSq/PZEk3J+dfHAuVCqVAzw8HX4Z2EkIHLW4b0qbl5NiwIQ0g3DHcC9klBst4BE mIGbR1at+Bq7pIijAaPaVqUWTYirQUkbo/o+nlx8lLSzIZd7N9x9vUzfOtRAjQxnn3Vh IExg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:sender:in-reply-to:references:date :message-id:subject:from:to; bh=U+0PtNcWVZh6Edq5pvLkCDuY+TmQ+DFs0xp51s1VTRI=; b=TvVLXqxFBmx6reK8jhSH+inBtJTkFYWZOjWGbc57ZleJ9mOZ+psMK6Fz4iH1IDzgGX UhX+2ZaBtBwi58DxZea9k1xbXe4yadjyFvKaX915vjpEiQrzo3gKljkEz4bAmlgJUQa6 ZMWkgSzbpuB5HIr4cNujHkUOge0Rx+HGmMPMnlaZAPDUkYeczwNfeu7+064xib41TOh2 mMAg6OP3wEQVudJYXqV847piDezzKKFcJX56O1Kg7NXfQhm05lCuBQ7eitr70ksUMZAy hfA9hVrTPpR0GbDlM7jGNsPzvCfo0o313ipx2/mN/zkKo0A4Cg+MmtOQianLbGpfnV+e kaBw== X-Gm-Message-State: AD7BkJJ9RHzKaUpk+z6l+eIma65qKUNvcL+UhtVHwK8DB7n6TT1u7FPUzY+bf21LQvCgrcxuBZbD1o6kv6JtEA== X-Received: by 10.50.43.161 with SMTP id x1mr11243017igl.47.1457830498063; Sat, 12 Mar 2016 16:54:58 -0800 (PST) Original-Sender: masanoriogino@gmail.com In-Reply-To: <20160313002140.GG9349@brightrain.aerifal.cx> X-Google-Sender-Auth: EqcxoL5Hp32EcZ5DFBCmHIDVGTE Xref: news.gmane.org gmane.linux.lib.musl.general:9601 Archived-At: 2016-03-13 9:21 GMT+09:00 Rich Felker : > On Sun, Mar 13, 2016 at 08:47:36AM +0900, Masanori Ogino wrote: >> Hello, >> >> While I work on my GSoC proposal, I doubt whether musl can be built >> without hardware atomic operation supports. >> >> Could we build musl without such instructions? >> If we could, what will happen with the features of musl? > > Atomic compare and swap (usually provided by either a direct cas > instruction or ll/sc pair type) is a hard requirement for musl. OK, I understood. > The normal profiles of riscv have at least ll/sc style and possibly cas > too. Yes, ll/sc style primitives are provided in A standard extension, according to the ISA spec v2.0, section 5.3. > Minimal profiles for microcontroller use lack it (this was a > mistake in the riscv ISA specification, IMO), so if supporting these > ISA levels is interesting, there are at least three options: > > 1. Have the kernel trap the unimplemented instructions and emulate > them. > > 2. Have userspace issue a system call to have the kernel mediate > atomic accesses. > > 3. Integrate atomic sequence restart with the scheduler: at scheduling > time, the kernel determines if the task being resumed was > interrupted in the middle of a sequence of instructions that's > supposed to be atomic, and if so, resets the program counter to the > beginning of the sequence. (This is how pre-v6 ARM and most SH > models work.) > > Option 3 offers by far the best performance but inherently only works > on uniprocessor. Options 1 and 2 could theoretically support SMP as > long as the kernel has some other way of ensuring mutual exclusion and > memory synchronization between the processors. > > Of course the best of all worlds is to have the kernel provide a vdso > function for atomic cas which it can then provide an optimal > implementation of for the particular processor being used. Then > baseline-ISA-level riscv binaries would use the vdso, and ones > targeting an ISA level that's known to have native atomic instructions > would use the inline instructions. OK, I will ask about the current status on the RISC-V sw-dev ML. Thank you for clarification. -- Masanori Ogino