From mboxrd@z Thu Jan 1 00:00:00 1970 X-Msuck: nntp://news.gmane.org/gmane.linux.lib.musl.general/9299 Path: news.gmane.org!not-for-mail From: David Edelsohn Newsgroups: gmane.linux.lib.musl.general Subject: Re: Re: musl libc for PPC64 Date: Wed, 10 Feb 2016 14:17:34 -0800 Message-ID: References: <20160208201802.GB9349@brightrain.aerifal.cx> <20160208225921.GD9349@brightrain.aerifal.cx> <20160208232945.GE9349@brightrain.aerifal.cx> <20160208234831.GI9915@port70.net> <20160209010336.GJ9915@port70.net> <20160209014549.GL9915@port70.net> <20160209015242.GF9349@brightrain.aerifal.cx> Reply-To: musl@lists.openwall.com NNTP-Posting-Host: plane.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 X-Trace: ger.gmane.org 1455142669 20098 80.91.229.3 (10 Feb 2016 22:17:49 GMT) X-Complaints-To: usenet@ger.gmane.org NNTP-Posting-Date: Wed, 10 Feb 2016 22:17:49 +0000 (UTC) Cc: musl@lists.openwall.com To: Rich Felker Original-X-From: musl-return-9312-gllmg-musl=m.gmane.org@lists.openwall.com Wed Feb 10 23:17:49 2016 Return-path: Envelope-to: gllmg-musl@m.gmane.org Original-Received: from mother.openwall.net ([195.42.179.200]) by plane.gmane.org with smtp (Exim 4.69) (envelope-from ) id 1aTd52-0004JC-88 for gllmg-musl@m.gmane.org; Wed, 10 Feb 2016 23:17:48 +0100 Original-Received: (qmail 26582 invoked by uid 550); 10 Feb 2016 22:17:46 -0000 Mailing-List: contact musl-help@lists.openwall.com; run by ezmlm Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-ID: Original-Received: (qmail 26556 invoked from network); 10 Feb 2016 22:17:45 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; bh=3T8ICv0uqLZWw2hDYUypiyJdHOmt4BK+NgEdHeAvAlw=; b=y6hphSAxf/qWX5waLdAA5J/7Rwgf6fXLVSQsVFUVLNXD8IWpcu3KjgRWIqJhaon9SS c3jwzi/NxrGQw2qu/p0asMrIFLNPGQqYtcPtdFnNoFGf0+Oaxy77dXzJU7jmsx/wUrlq giXidtgAhuIKGK9Db49Dlg2uCrd0ntE5d/jZSjMdVSC6LFo3JzXemOlcr5qtubT4PUSN Y8M83D6dGmpzob5ZU1C95Z2HAt/Gs8PFf3hF8hM5bYeFfspLTfortrbKQGyyGQlXxq7o Te2d5ObVLM4wgPC6D1sBnRSi/eYurdV5a15ajanvZoZxxDEeo0Ed8zSgNuQ2+6drwAbp 8eXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:in-reply-to:references:date :message-id:subject:from:to:cc:content-type; bh=3T8ICv0uqLZWw2hDYUypiyJdHOmt4BK+NgEdHeAvAlw=; b=AymGV+5VjgxfEbIAn1pzMOMRY0+ApmUc7NEb6vqSb5fP4F8WBVL3ACD3MNgPHWyS8H mLkZ/HQmOU0UCINOY77sTwDqUfCszTNiivRrcptW0FuHgv2lDQOYCMg57jU1olOj0Iy7 13IFiZX911sb8FwBYb2uDSihrvHoHkMSaFjfMPknX7jJAVs0urWO95VFwsW4GI4fl7Ir n1oRV+8VjKtklr6wFgyF1VMJkqWYM9TJp7+79vakYxqpgM1SaUMSBSmxe/l2xMKuAl+T G52DXBV+2MYcigOi22ViZk50s+zlU45dRw0ozw2NthCCZAIoedC5Hm/WuosO1z3tdbUH jGig== X-Gm-Message-State: AG10YOQbcO57Hroi68V01Djm5WgShoof+Im+9BR6QM7l6HMdMyFRn1QOCLHHEV39jM57sbfrW8egvoc7fxI+VA== X-Received: by 10.25.7.201 with SMTP id 192mr14165539lfh.107.1455142654674; Wed, 10 Feb 2016 14:17:34 -0800 (PST) In-Reply-To: <20160209015242.GF9349@brightrain.aerifal.cx> Xref: news.gmane.org gmane.linux.lib.musl.general:9299 Archived-At: On Mon, Feb 8, 2016 at 5:52 PM, Rich Felker wrote: > On Tue, Feb 09, 2016 at 02:45:50AM +0100, Szabolcs Nagy wrote: >> * David Edelsohn [2016-02-08 20:16:25 -0500]: >> > On Mon, Feb 8, 2016 at 8:03 PM, Szabolcs Nagy wrote: >> > > * Szabolcs Nagy [2016-02-09 00:48:31 +0100]: >> > >> * Rich Felker [2016-02-08 18:29:45 -0500]: >> > >> > On Mon, Feb 08, 2016 at 06:24:27PM -0500, David Edelsohn wrote: >> > >> > > I'm not sure what you mean. The software emulation assumes the >> > >> > > hardware support is not present. It doesn't mirror back the state to >> > >> > > the processor in 64 bit mode. But the emulation is fully IEEE128 >> > >> > > compliant. >> > >> > >> > >> > if fesetround(FE_DOWNWARD) succeeds but then long double math still >> > >> > rounds to nearest, that's not IEEE compliant. >> > >> > >> > >> > The big obstacle to having fenv with softfloat on fully-softfloat >> > >> > archs is the lack of register state for the rounding mode and >> > >> > exception flags, so it should be possible to do this right as long as >> > >> > the cpu has status/mode registers for single/double, which the >> > >> > soft-quad code can then access/set. If this isn't done right already >> > >> > we could either try to get it fixed in libgcc or punt and go with >> > >> > ld64. >> > >> > >> > >> >> > >> it seems to be supported >> > >> https://gcc.gnu.org/git/?p=gcc.git;a=blob;f=libgcc/config/rs6000/sfp-machine.h;h=75d5e1a2d522e0a3d3c5b0463fcfe9b054f7c263;hb=HEAD#l107 >> > >> >> > >> so we can implement iso c annex f with 128 bit long doubles. >> > > >> > > hm it seems, this is only for the __float128 type >> > > which will be new in gcc-6. >> > > >> > > i don't see how to configure gcc with ieee128 long double. >> > > (other than using the debug option -mabi=ieeelongdouble) >> > > >> > > so if musl goes with ieee128 long double abi then it will >> > > only work with latest gcc. >> > >> > The musl libc dynamic linking support only was added to the latest GCC. >> > >> >> (resend with correct to:) >> >> musl has a gcc wrapper that changes the specs file and then >> it works even with gcc-3 (on x86 and glibc host without c++). >> >> we also have patches for gcc releases going back to gcc-4.7 > > Indeed. Just patching in the dynamic linker name and a few other > details to make gcc target musl properly is small and can be done for > any gcc version. Patching in ieee quad or ABI changes is non-trivial > though. How much would it be for a knowledgeable member of the musl libc community to provide basic enablement for powerpc64 ELFv2 -- either initially disable long double or use IEEE 128? We can think about optimizations later. Thanks, David