From mboxrd@z Thu Jan 1 00:00:00 1970 X-Msuck: nntp://news.gmane.org/gmane.linux.lib.musl.general/11633 Path: news.gmane.org!.POSTED!not-for-mail From: David Edelsohn Newsgroups: gmane.linux.lib.musl.general Subject: Re: [PATCH] powerpc64le: Add single instruction math functions Date: Thu, 29 Jun 2017 21:07:16 -0400 Message-ID: References: <594DB66E.7030009@adelielinux.org> <594DDEC6.8030200@adelielinux.org> <594EFC63.3000707@adelielinux.org> <20170625001024.GA1627@brightrain.aerifal.cx> <20170629160544.GE1627@brightrain.aerifal.cx> <20170629175926.GF1627@brightrain.aerifal.cx> Reply-To: musl@lists.openwall.com NNTP-Posting-Host: blaine.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" X-Trace: blaine.gmane.org 1498784850 22079 195.159.176.226 (30 Jun 2017 01:07:30 GMT) X-Complaints-To: usenet@blaine.gmane.org NNTP-Posting-Date: Fri, 30 Jun 2017 01:07:30 +0000 (UTC) To: musl@lists.openwall.com Original-X-From: musl-return-11646-gllmg-musl=m.gmane.org@lists.openwall.com Fri Jun 30 03:07:27 2017 Return-path: Envelope-to: gllmg-musl@m.gmane.org Original-Received: from mother.openwall.net ([195.42.179.200]) by blaine.gmane.org with smtp (Exim 4.84_2) (envelope-from ) id 1dQkP8-0005Yk-1R for gllmg-musl@m.gmane.org; Fri, 30 Jun 2017 03:07:26 +0200 Original-Received: (qmail 20266 invoked by uid 550); 30 Jun 2017 01:07:29 -0000 Mailing-List: contact musl-help@lists.openwall.com; run by ezmlm Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-ID: Original-Received: (qmail 20242 invoked from network); 30 Jun 2017 01:07:29 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to; bh=DdafGJ2d3ntrvt8iq8zkcXBqXH08BVWlskQwMsZfb5Y=; b=Rg+MnNCPJfsKvh2q1aCQMkfNaFCvZSIZZcoHOi7VdnWG+8OEDqqLV5P1pYDy0cTFOQ SBxiAXbnH5ZZ2lAI4f57zhk4ZEHusrQJCMIVQwVQ6zEh+V0Z0N1AUD3392Kh3CH5d9rw k+Ttn+T6db5VjZ6bbYHt+bV+iXFRFYEyGlEuf41CRhl/YfiqHFS5LQmumrfA9eEgD7AD bQkjZ2HMEnxnPyVORGs33JDHRkkXz7guZ6KNQSALM1zn//tKN8+JFhuaeIi9ngbMNLNG gmFdMNrEOU4wJg9KjBpEkD9+elqVoyH9xtfkSLZL4QtVxWUYmriuVL2r/c92iVxwafpS 8gRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to; bh=DdafGJ2d3ntrvt8iq8zkcXBqXH08BVWlskQwMsZfb5Y=; b=bMVUuMLZQAglwcQDeG5ct1i6FftY9alwFCC1JU6C536A6tOgigaZ4l8uS/L7BFS1wi zjUALlKlxCGqtytLcGhQWnnuRSXCwbVwrlkMQ3B+ZRoeaXUbEbhzwRmDQu8g51Y84ONb f7lRo5a7dzGoRgn2WvqWQRt25GivQ7AVrCyAbrrdi71qFixJl4CtP7w2rlawsP9S7BuE OF4/VYDDE5+gzhtbai6HTA6LauxIwz//BPKuBn+GhLNER+1F0ZODy6RTGC/Te0cu66rI Rg/1NnYZQYb8xOg8y9ed2Cw6YNXxxAuaXBeSR/NTckj7NmN0d4J986p6qLO7rsXFgG8y qMbg== X-Gm-Message-State: AKS2vOzJLEfdicwdll6NZ4iAiana8hl0dfxe4SXVbUONcNzAGHCRIIua iRRujemgNcpsV/NY3oQb8gbNjrVX4A== X-Received: by 10.237.45.3 with SMTP id h3mr22359184qtd.110.1498784837064; Thu, 29 Jun 2017 18:07:17 -0700 (PDT) In-Reply-To: <20170629175926.GF1627@brightrain.aerifal.cx> Xref: news.gmane.org gmane.linux.lib.musl.general:11633 Archived-At: On Thu, Jun 29, 2017 at 1:59 PM, Rich Felker wrote: > On Thu, Jun 29, 2017 at 01:00:51PM -0400, David Edelsohn wrote: >> >> A colleague of mine reminded me that ELFv2 ABI specifies POWER8 as the >> >> minimum hardware (not little-endian). >> > >> > This is a gratuitous requirement and has nothing to do with the >> > meaning of ELFv2 we're using (and likewise not with the gcc >> > --with-abi=elfv2). >> >> 2.1.1. Processor Architecture >> >> This ABI is predicated on, at a minimum, Power ISA version 2.7 and >> contains additional implementation characteristics. > > Yes, I understand that it's there but this "requirement" is orthogonal > to the actual interface boundaries the ABI defines. ARM's EABI has a > similar gratuitous baseline of v4t; the compiler can satisfy all the > interface boundary requirements even on v4 and probably lower if it > wants to, but nobody has implemented that. > >> >> The implementation of ELFv2 can >> >> operate on earlier hardware, but binaries may not be forward >> >> compatible because of VSX. Because of the calling convention of VSX >> >> registers in ELFv2, the stack may be corrupted if an application built >> >> without VSX support is linked with a library that does support VSX. >> >> One cannot mix and match musl libc built for POWER4 or PPC970 and musl >> >> libc built for POWER7. >> > >> > I don't think this is accurate. If it is then it's a serious bug we >> > need to fix, and it should have been discussed at the time the port >> > was added... >> >> This is not an implementation detail in the library, it is the calling >> convention in the compilers. >> >> > >> > Can you provide a citation for the usage of VSX registers in the >> > calling convention, and how you think that affects the stack? >> >> Table 2.22 Vector Register Roles in Section 2.2.1.1 Register Roles. >> The definition of volatile and non-volatile registers for vector >> registers affects the amount of stack allocated and the saving of >> non-volatile registers. > > Are you saying the caller has to allocate space that the callee might > use to preseve call-saved registers it wants to use, and that the > amount saved depends on ISA level? If so I'll look for the associated > logic in GCC and see what it's doing. If that's the case it should be > reserving space regardless of whether it's built for an ISA level with > the registers or not. I thought that there was a change in the volatile status of the VSR registers. I'm don't remember if this affected the stack frame or stdarg. There was some corner case. How can the toolchain save space for registers that it doesn't know about? - David