From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on inbox.vuxu.org X-Spam-Level: X-Spam-Status: No, score=-3.1 required=5.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H4,RCVD_IN_MSPIKE_WL autolearn=ham autolearn_force=no version=3.4.4 Received: from second.openwall.net (second.openwall.net [193.110.157.125]) by inbox.vuxu.org (Postfix) with SMTP id 34403225D5 for ; Wed, 24 Jul 2024 00:50:15 +0200 (CEST) Received: (qmail 27802 invoked by uid 550); 23 Jul 2024 22:50:09 -0000 Mailing-List: contact musl-help@lists.openwall.com; run by ezmlm Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-ID: Reply-To: musl@lists.openwall.com Received: (qmail 23854 invoked from network); 23 Jul 2024 22:47:58 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=alexrp.com; s=alexrp; t=1721774870; x=1722379670; darn=lists.openwall.com; h=content-transfer-encoding:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=W0OuNzcny+9VJ6998Qe7w7dAkijEUi4X33z/Hk+qaMA=; b=IKxzcGjzA9gxO31FXxEC7RY6IFB8OWHuJ2AckZ5io6FIe6Sgvd+PWsQkICX+d77uE1 /FHO310rM2K/0soLyHe/B2NuFh3qELSBgh0hr3cDvZEb7PLhvhKcGHZN9fU98n9eoS1K jdKVcUJxZip70+xuzZYOdqjBPJhhDE/dcbN3ajhfYzoA+uFALoZhsuIJBOpAW8F045OP 2yC7jo2tZmdBE6KkOl6u23MLHkZNCfV7FJZ3RmsNOpszFEEydZH5soiG+p7Y6HhvJkhT mbczRaJL3CyuntYHVrf9rPcGVf8p6JNo57Lp8ExFXHWZ4yZONFY8jvTX3Fnw+e+ySz2U CaFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1721774870; x=1722379670; h=content-transfer-encoding:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=W0OuNzcny+9VJ6998Qe7w7dAkijEUi4X33z/Hk+qaMA=; b=rXss+ggKfe5aagpEVbd1COLrWIEnXDGOQ2oor7j4ICU16GzIVGezKvjv19l4DfSqrS JCjBsd6YZP6/dXyIhDTIc7udXFBkuMNSbOFQ+PsTp09VsNQykgZCfxy3xZLCklwkTeAQ Km2oYD/qvuZK9UNzkeMk+0Wzz8Mi6wMjRXF2+sh7BYikV1ibVzTO56TIQj3XGs5k/SI+ UTHGMJlgSlKdelb4JEOEQv1Sm+IhsM3+6LHShA68WuXknmww3GTsSaDp2yd98bYDqpA5 0TvsJ7S3LmpOLL2r1Tda558DuCAdljm8dP7VKF4zYpnmbBPh9HvRdupR6e7iwge1Z0xG vxSQ== X-Forwarded-Encrypted: i=1; AJvYcCWQh3C3PKyjSjmNnKviG1Z+nszQUtFkX2PbHRjbIrSW2jyk1+bh7QGMunaq7kDPq2fv8nZ39j4Y7t0VezM8ayV95qh4jJIXGA== X-Gm-Message-State: AOJu0YxHO1s6cT88SPAmtMqpXQhuWgFPK0LYEEClptZDZlxY+hqgVAbq +PLqAjhRXLFABTPsNt3hOGcahCk8jLhmpVT/uZLxW9ux0pmxkXamv5efQWSBwZB4CHuAtVCyXnK W3VDJxkSbe5hIE8dbfstLQRo/nFBxDP1liWV/03OVQioScrB5 X-Google-Smtp-Source: AGHT+IHcb48RGvZ4IZvArTxLbRib5KLq0vvlTuJCbp944usLVJjIqAaNxPsg+sHFfG3FOvR5wJ2DXB98rWpBzt0AQw8= X-Received: by 2002:a5d:6d08:0:b0:367:9904:e6b9 with SMTP id ffacd0b85a97d-369bb0a0e12mr9716158f8f.44.1721774870220; Tue, 23 Jul 2024 15:47:50 -0700 (PDT) MIME-Version: 1.0 References: <20240629020434.488975-1-alex@alexrp.com> <20240723212241.GV3766212@port70.net> In-Reply-To: <20240723212241.GV3766212@port70.net> From: =?UTF-8?Q?Alex_R=C3=B8nne_Petersen?= Date: Wed, 24 Jul 2024 00:47:14 +0200 Message-ID: To: =?UTF-8?Q?Alex_R=C3=B8nne_Petersen?= , musl@lists.openwall.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Subject: Re: [musl] [PATCH] riscv: Fix setjmp assembly when compiling for ilp32f/lp64f. On Tue, Jul 23, 2024 at 11:22=E2=80=AFPM Szabolcs Nagy wro= te: > > * Alex R=C3=B8nne Petersen [2024-06-29 04:04:34 +0200]: > > To keep things simple, I just changed the instruction mnemonics appropr= iately, > > rather than adding complexity by changing the buffer size/offsets based= on ABI. > > > > Signed-off-by: Alex R=C3=B8nne Petersen > > fwiw this looks good to me. > > the only weirdness is that the math code uses __riscv_flen > and this code __riscv_float_abi*. i don't know if there > is semantic difference. `__riscv_flen` tells you the width of the FP registers on the target CPU. This is semantically distinct from `__riscv_float_abi`. For example, while it would probably be a bit silly, there's no particular reason why I couldn't target the LP64F ABI on an RV64IMAFDC machine. In that case, no code needs to concern itself with the upper bits of the FP registers. I took a quick peek at some of the `__riscv_flen` checks in musl. They look ok. They're checking the capabilities of the machine for the purposes of performing a computation; they're not making ABI decisions. In my silly example above, if I tell the compiler to do so with `-march=3Drv64...d`, it would theoretically be fine for the compiler to generate double-precision float instructions for computations as long as values are passed/returned according to LP64F rules. > > > --- > > src/setjmp/riscv32/longjmp.S | 30 ++++++++++++++++++------------ > > src/setjmp/riscv32/setjmp.S | 30 ++++++++++++++++++------------ > > src/setjmp/riscv64/longjmp.S | 30 ++++++++++++++++++------------ > > src/setjmp/riscv64/setjmp.S | 30 ++++++++++++++++++------------ > > 4 files changed, 72 insertions(+), 48 deletions(-) > > > > diff --git a/src/setjmp/riscv32/longjmp.S b/src/setjmp/riscv32/longjmp.= S > > index f9cb3318..b4e5458d 100644 > > --- a/src/setjmp/riscv32/longjmp.S > > +++ b/src/setjmp/riscv32/longjmp.S > > @@ -23,18 +23,24 @@ longjmp: > > lw ra, 52(a0) > > > > #ifndef __riscv_float_abi_soft > > - fld fs0, 56(a0) > > - fld fs1, 64(a0) > > - fld fs2, 72(a0) > > - fld fs3, 80(a0) > > - fld fs4, 88(a0) > > - fld fs5, 96(a0) > > - fld fs6, 104(a0) > > - fld fs7, 112(a0) > > - fld fs8, 120(a0) > > - fld fs9, 128(a0) > > - fld fs10, 136(a0) > > - fld fs11, 144(a0) > > +#ifdef __riscv_float_abi_double > > +#define FLX fld > > +#else > > +#define FLX flw > > +#endif > > + > > + FLX fs0, 56(a0) > > + FLX fs1, 64(a0) > > + FLX fs2, 72(a0) > > + FLX fs3, 80(a0) > > + FLX fs4, 88(a0) > > + FLX fs5, 96(a0) > > + FLX fs6, 104(a0) > > + FLX fs7, 112(a0) > > + FLX fs8, 120(a0) > > + FLX fs9, 128(a0) > > + FLX fs10, 136(a0) > > + FLX fs11, 144(a0) > > #endif > > > > seqz a0, a1 > > diff --git a/src/setjmp/riscv32/setjmp.S b/src/setjmp/riscv32/setjmp.S > > index 8a75cf55..5a1a41ef 100644 > > --- a/src/setjmp/riscv32/setjmp.S > > +++ b/src/setjmp/riscv32/setjmp.S > > @@ -23,18 +23,24 @@ setjmp: > > sw ra, 52(a0) > > > > #ifndef __riscv_float_abi_soft > > - fsd fs0, 56(a0) > > - fsd fs1, 64(a0) > > - fsd fs2, 72(a0) > > - fsd fs3, 80(a0) > > - fsd fs4, 88(a0) > > - fsd fs5, 96(a0) > > - fsd fs6, 104(a0) > > - fsd fs7, 112(a0) > > - fsd fs8, 120(a0) > > - fsd fs9, 128(a0) > > - fsd fs10, 136(a0) > > - fsd fs11, 144(a0) > > +#ifdef __riscv_float_abi_double > > +#define FSX fsd > > +#else > > +#define FSX fsw > > +#endif > > + > > + FSX fs0, 56(a0) > > + FSX fs1, 64(a0) > > + FSX fs2, 72(a0) > > + FSX fs3, 80(a0) > > + FSX fs4, 88(a0) > > + FSX fs5, 96(a0) > > + FSX fs6, 104(a0) > > + FSX fs7, 112(a0) > > + FSX fs8, 120(a0) > > + FSX fs9, 128(a0) > > + FSX fs10, 136(a0) > > + FSX fs11, 144(a0) > > #endif > > > > li a0, 0 > > diff --git a/src/setjmp/riscv64/longjmp.S b/src/setjmp/riscv64/longjmp.= S > > index 41e2d210..982475c7 100644 > > --- a/src/setjmp/riscv64/longjmp.S > > +++ b/src/setjmp/riscv64/longjmp.S > > @@ -23,18 +23,24 @@ longjmp: > > ld ra, 104(a0) > > > > #ifndef __riscv_float_abi_soft > > - fld fs0, 112(a0) > > - fld fs1, 120(a0) > > - fld fs2, 128(a0) > > - fld fs3, 136(a0) > > - fld fs4, 144(a0) > > - fld fs5, 152(a0) > > - fld fs6, 160(a0) > > - fld fs7, 168(a0) > > - fld fs8, 176(a0) > > - fld fs9, 184(a0) > > - fld fs10, 192(a0) > > - fld fs11, 200(a0) > > +#ifdef __riscv_float_abi_double > > +#define FLX fld > > +#else > > +#define FLX flw > > +#endif > > + > > + FLX fs0, 112(a0) > > + FLX fs1, 120(a0) > > + FLX fs2, 128(a0) > > + FLX fs3, 136(a0) > > + FLX fs4, 144(a0) > > + FLX fs5, 152(a0) > > + FLX fs6, 160(a0) > > + FLX fs7, 168(a0) > > + FLX fs8, 176(a0) > > + FLX fs9, 184(a0) > > + FLX fs10, 192(a0) > > + FLX fs11, 200(a0) > > #endif > > > > seqz a0, a1 > > diff --git a/src/setjmp/riscv64/setjmp.S b/src/setjmp/riscv64/setjmp.S > > index 51249672..0795bf7d 100644 > > --- a/src/setjmp/riscv64/setjmp.S > > +++ b/src/setjmp/riscv64/setjmp.S > > @@ -23,18 +23,24 @@ setjmp: > > sd ra, 104(a0) > > > > #ifndef __riscv_float_abi_soft > > - fsd fs0, 112(a0) > > - fsd fs1, 120(a0) > > - fsd fs2, 128(a0) > > - fsd fs3, 136(a0) > > - fsd fs4, 144(a0) > > - fsd fs5, 152(a0) > > - fsd fs6, 160(a0) > > - fsd fs7, 168(a0) > > - fsd fs8, 176(a0) > > - fsd fs9, 184(a0) > > - fsd fs10, 192(a0) > > - fsd fs11, 200(a0) > > +#ifdef __riscv_float_abi_double > > +#define FSX fsd > > +#else > > +#define FSX fsw > > +#endif > > + > > + FSX fs0, 112(a0) > > + FSX fs1, 120(a0) > > + FSX fs2, 128(a0) > > + FSX fs3, 136(a0) > > + FSX fs4, 144(a0) > > + FSX fs5, 152(a0) > > + FSX fs6, 160(a0) > > + FSX fs7, 168(a0) > > + FSX fs8, 176(a0) > > + FSX fs9, 184(a0) > > + FSX fs10, 192(a0) > > + FSX fs11, 200(a0) > > #endif > > > > li a0, 0 > > -- > > 2.40.1