From mboxrd@z Thu Jan 1 00:00:00 1970 X-Msuck: nntp://news.gmane.org/gmane.linux.lib.musl.general/12749 Path: news.gmane.org!.POSTED!not-for-mail From: Andre McCurdy Newsgroups: gmane.linux.lib.musl.general Subject: Re: [PATCH 2/2] arm: enable a_ll and a_sc helper functions when building for ARMv6T2 Date: Thu, 19 Apr 2018 13:38:51 -0700 Message-ID: References: <1524102704-8973-1-git-send-email-armccurdy@gmail.com> <1524102704-8973-3-git-send-email-armccurdy@gmail.com> <20180419163851.GL3094@brightrain.aerifal.cx> <20180419192519.GN3094@brightrain.aerifal.cx> Reply-To: musl@lists.openwall.com NNTP-Posting-Host: blaine.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" X-Trace: blaine.gmane.org 1524170220 16661 195.159.176.226 (19 Apr 2018 20:37:00 GMT) X-Complaints-To: usenet@blaine.gmane.org NNTP-Posting-Date: Thu, 19 Apr 2018 20:37:00 +0000 (UTC) To: musl@lists.openwall.com Original-X-From: musl-return-12765-gllmg-musl=m.gmane.org@lists.openwall.com Thu Apr 19 22:36:56 2018 Return-path: Envelope-to: gllmg-musl@m.gmane.org Original-Received: from mother.openwall.net ([195.42.179.200]) by blaine.gmane.org with smtp (Exim 4.84_2) (envelope-from ) id 1f9GIa-0004Ev-CP for gllmg-musl@m.gmane.org; Thu, 19 Apr 2018 22:36:56 +0200 Original-Received: (qmail 19701 invoked by uid 550); 19 Apr 2018 20:39:04 -0000 Mailing-List: contact musl-help@lists.openwall.com; run by ezmlm Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-ID: Original-Received: (qmail 19683 invoked from network); 19 Apr 2018 20:39:03 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to; bh=DBOHrY1/r5/kk6VFfKV7oSMbWfemqoddpHcalwtAx5E=; b=U07MP4QzoiyLnCl4litqr9mmpKwbkO3TmxiwN1RPHRYLHRH+deDit93fvhai+ip6Zz CQZDrvqbTK3CaavI+Ah6KPDfyKoF8kqjajjUpOmylUBkWlHi2L0ZzcFymC8gWSiBdGxP FI5jrOy0eCkt8ovk8+gbBcI9hRRc2y/hUkegdjrQQ0Hp0g/vL9MKFkEw+0Ot5r74z+oT VKg985Ndei0FGu2v7M33w+g367wS2OehdXhmf+9vJJAKIZKdA3ljTKDhd3ZyDNwI0nWq Eh7Oi45bopCNyv8kmdn5Tij48DJiJxH3SXLJDcIQMPlCSIQHKHZdJDR+UOvnYwjCCLRC /weg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to; bh=DBOHrY1/r5/kk6VFfKV7oSMbWfemqoddpHcalwtAx5E=; b=gRJ/08RYntGQMYtkjr7fL611FgmuC1GgovU722Nl7Sn9rEpp7X5uTqZJ9caDc7H0to iT6Yo4wIwe9Ah7vYr7zofxeOgiHyjP9PQYyz/4/1mZOMGjHJIjRNr3TsUs1cWRbjoJh5 bjRgr/KswaDwaVaztX3/+l99rWn8sGLfJEdRot3c/nGVg+wZJQp9IcSU2nBOcWidFd8b 0NSjOyyPBCqbhrRdYi5LuGOZFQjlG5+Ezv/MIYdNtICCvnz8MVqfOrHbHs27svrABGM8 5u1stC8OcFBnSsnI4pIoGDDRtsEn7YKUBouCEAAaZsxGger/I7DvTP8pXBxum+IcF2w5 1sDQ== X-Gm-Message-State: ALQs6tAK0jfIlu6GErrOSP8DK7s2Wm/jRTztNRD2tKll/pb7MlylGQ6Z YyvrrzLWDTLXNTOityBvteCWG4QupKyMeP0S0vnggA== X-Google-Smtp-Source: AB8JxZqryScFvAk1Y1Z34ydoTbqGbBxpKAy2UfU+moqmgiW1yzAwlvTAIS2G5SJAIuVrReUyOBFLf5ctMF2DzXD0Zdc= X-Received: by 10.28.90.197 with SMTP id o188mr140041wmb.151.1524170331626; Thu, 19 Apr 2018 13:38:51 -0700 (PDT) In-Reply-To: <20180419192519.GN3094@brightrain.aerifal.cx> Xref: news.gmane.org gmane.linux.lib.musl.general:12749 Archived-At: On Thu, Apr 19, 2018 at 12:25 PM, Rich Felker wrote: > On Thu, Apr 19, 2018 at 12:14:51PM -0700, Andre McCurdy wrote: >> On Thu, Apr 19, 2018 at 9:38 AM, Rich Felker wrote: >> > On Wed, Apr 18, 2018 at 06:51:44PM -0700, Andre McCurdy wrote: >> >> ARMv6 cores with support for Thumb2 can take advantage of the "ldrex" >> >> and "strex" based implementations of a_ll and a_sc. >> >> --- >> >> arch/arm/atomic_arch.h | 2 +- >> >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> >> >> diff --git a/arch/arm/atomic_arch.h b/arch/arm/atomic_arch.h >> >> index 5ff1be1..62458b4 100644 >> >> --- a/arch/arm/atomic_arch.h >> >> +++ b/arch/arm/atomic_arch.h >> >> @@ -8,7 +8,7 @@ extern uintptr_t __attribute__((__visibility__("hidden"))) >> >> __a_cas_ptr, __a_barrier_ptr; >> >> >> >> #if ((__ARM_ARCH_6__ || __ARM_ARCH_6K__ || __ARM_ARCH_6KZ__ || __ARM_ARCH_6ZK__) && !__thumb__) \ >> >> - || __ARM_ARCH_7A__ || __ARM_ARCH_7R__ || __ARM_ARCH >= 7 >> >> + || __ARM_ARCH_6T2__ || __ARM_ARCH_7A__ || __ARM_ARCH_7R__ || __ARM_ARCH >= 7 >> >> >> >> #define a_ll a_ll >> >> static inline int a_ll(volatile int *p) >> > >> > I'm merging this along with the others, but there is some concern that >> > our use of a_ll/a_sc might not actually be valid on most or all of the >> > archs we currently use it on. Depending on how this turns out it might >> > all be removed at some later time. >> >> That sound ominous. What's the concern? > > Originally ARM didn't document it, but reportedly it's now documented > somewhere that the ll and sc operations have certain strong conditions > on how they're used. RISC-V's and maybe other archs' also have similar > conditions. They're something along the lines of (from my memory): > > - no intervening loads or stores between ll and sc > - limit on number of instructions between ll and sc > - no jumps or branches between ll and sc > > and there is no way to guarantee these kinds of conditions when the > compiler is free to move the ll and sc asm blocks independently. > > From a practical standpoint, it looks like the conditions are overly > conservative and designed to allow cpu implementations with very bad > cache designs (direct-mapped, small, etc.) but they may turn out to be > relevant so we need to evaluate if we need to care about this... Thanks. Google found the following: https://stackoverflow.com/questions/10812442/arm-ll-sc-exclusive-access-by-register-width-or-cache-line-width http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dht0008a/CJAGCFAF.html It takes some digesting, but I don't see an immediate red flag. An instruction sequence which Interleaves two ll sc sequences would seem to be an issue, but we don't do that. A uniprocessor system running without data caching could be problem (implementation dependent). But if I read correctly, the failure mode would be that sc would always fail and therefore the system would deadlock, so it won't be a subtle failure?