From mboxrd@z Thu Jan 1 00:00:00 1970 X-Msuck: nntp://news.gmane.org/gmane.linux.lib.musl.general/12562 Path: news.gmane.org!.POSTED!not-for-mail From: Andre McCurdy Newsgroups: gmane.linux.lib.musl.general Subject: Re: clz instruction is unavailable for Thumb1 Date: Tue, 27 Feb 2018 19:00:58 -0800 Message-ID: References: <1799b81c-10d6-c2ac-4411-6ee9808f2356@codeaurora.org> <20180228010110.GS1436@brightrain.aerifal.cx> <20180228021641.GT1436@brightrain.aerifal.cx> Reply-To: musl@lists.openwall.com NNTP-Posting-Host: blaine.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" X-Trace: blaine.gmane.org 1519786752 12587 195.159.176.226 (28 Feb 2018 02:59:12 GMT) X-Complaints-To: usenet@blaine.gmane.org NNTP-Posting-Date: Wed, 28 Feb 2018 02:59:12 +0000 (UTC) To: musl@lists.openwall.com Original-X-From: musl-return-12578-gllmg-musl=m.gmane.org@lists.openwall.com Wed Feb 28 03:59:08 2018 Return-path: Envelope-to: gllmg-musl@m.gmane.org Original-Received: from mother.openwall.net ([195.42.179.200]) by blaine.gmane.org with smtp (Exim 4.84_2) (envelope-from ) id 1eqrxT-0002t0-Fr for gllmg-musl@m.gmane.org; Wed, 28 Feb 2018 03:59:07 +0100 Original-Received: (qmail 28114 invoked by uid 550); 28 Feb 2018 03:01:11 -0000 Mailing-List: contact musl-help@lists.openwall.com; run by ezmlm Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-ID: Original-Received: (qmail 28095 invoked from network); 28 Feb 2018 03:01:11 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to; bh=3bDYbLE7S+crGsZHde1/bAMAjzP+xyfA1t+qxV9LUcQ=; b=ucEjq2xI65ISHuLA52Goia6GMUvomznLDQCBecmN2nsPga8171S7i3R5EcWRYfgR2U GPPkO5ndycizX8vC+uHKWG1/iiwX8XFo/issBHcx5SIO6oLX40W9q/0+C/ygYyIaCLqI sz8h6JjhtzE+Vpr9HYr/y4UF5v2NM9bjuQexcTLaNfFn6ySnMNdM15tLz1I76McjLlct 4SylP5BFQCejNA+duvdsFbWwFj+lPTg5tg1hJDO+mWa4UzqWucoeRVYnmQz77TMqlANK RCAkjaXYqzm+DHZuDSf5SVHZ+joPcdrKH/42I1flswKRlsuqmBen8ARz++CR5GdNKFYI +wUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to; bh=3bDYbLE7S+crGsZHde1/bAMAjzP+xyfA1t+qxV9LUcQ=; b=WJYhsc7wtiClDfvhNWVLBBsSjp3eEO9tlreeEEY4E8IFSaIgSLpgdvEIaOEwWWuxtT 3XnvhxHumW6/L4FPLHPXQRNKEl4Y7nfDxfH/wMb4OcQUP/6nTHIj/MAVD4CbdZ/VRMRO mi7T2Ah2BdQ2y7ixWDEbKAb1z5jSCBkhlrLVoW1OycfCpU+771UcWLqu4kv57yAvpuwM hOMYy0uAuMLMVkKMtdDV0CWGLzCUFRG57/Z7a01hH4gCkiLWNI41oiBPFGBKUVzD3JGD GvhNzWWN/hZpuys/1IexEsvCB89d+OF90zRXCjIw2I3a/DpwMEdHKBo445ERe6qeE5uc lgRA== X-Gm-Message-State: APf1xPCPrEz1zsE7Iona9EOdcpbwQ7AcZKHlgFCUaj/w4yP8WZ8xXNbC 7EcRpG5wqHDR7yrg3zNYzBq49O7NwaeYXS5O2k+RlA== X-Google-Smtp-Source: AG47ELtXpS2GqS9lPnaJsFyvZBUk2IhcjZosEb8ImW3DN/63GnSnHYvzCY4ZWiafBVGMYixQCeBLzUOfs5NXRVOp93s= X-Received: by 10.28.170.205 with SMTP id t196mr6423687wme.42.1519786859569; Tue, 27 Feb 2018 19:00:59 -0800 (PST) In-Reply-To: <20180228021641.GT1436@brightrain.aerifal.cx> Xref: news.gmane.org gmane.linux.lib.musl.general:12562 Archived-At: On Tue, Feb 27, 2018 at 6:16 PM, Rich Felker wrote: > On Tue, Feb 27, 2018 at 05:26:13PM -0800, Andre McCurdy wrote: >> On Tue, Feb 27, 2018 at 5:01 PM, Rich Felker wrote: >> > On Tue, Feb 27, 2018 at 04:37:15PM -0800, Andre McCurdy wrote: >> >> On Tue, Feb 27, 2018 at 4:03 PM, Zhao, Weiming wrote: >> >> > In arch/arm/atomic_arch.h, it checks for __ARM_ARCH >= 5, which is not >> >> > sufficient. >> >> > >> >> > for example, for armv6-m, it only support Thumb1, which doesn't include clz. >> >> > >> >> > Suggest to check if it's building for thumb1: >> >> >> >> Musl does not currently support Thumb 1. >> > >> > I forget what the situation with v6-m is, and whether/how it could be >> > supportable. Is it really thumb1 or some thumb2 subset that fills >> > deficiencies? >> >> It's Thumb1 plus BL, DMB, DSB, ISB, MRS and MSR from Thumb2. > > So that covers barrier but not atomics or thread pointer or syscalls, > right? Thumb1 can make syscalls, but armv6-m has no atomics (the RTOS style alternative being to disable interrupts around critical sections) and no thread pointer (no coprocessors at all). > I'm not seeing how arm with only thumb1 plus the above can be a > viable platform musl could run on, but maybe there are some kernel > mechanisms to help..? I don't know if it's even possible to run a Linux kernel on these devices. >> > My recollection was that thumb1 lacks atomics, barriers, >> > thread-pointer loading, and maybe even syscalls, and since the >> > kuser_helper addresses are arm addresses, you can't even use them to >> > get the missing functionality. >> > >> > Rich >> > >> >> > diff --git a/arch/arm/atomic_arch.h b/arch/arm/atomic_arch.h >> >> > index c5c56f8..e3cb66a 100644 >> >> > --- a/arch/arm/atomic_arch.h >> >> > +++ b/arch/arm/atomic_arch.h >> >> > @@ -82,7 +82,7 @@ static inline void a_crash() >> >> > : : : "memory"); >> >> > } >> >> > >> >> > -#if __ARM_ARCH >= 5 >> >> > +#if __ARM_ARCH >= 5 && !(defined(__thumb__) && !defined(__thumb2)) >> >> >