From mboxrd@z Thu Jan 1 00:00:00 1970 X-Msuck: nntp://news.gmane.org/gmane.linux.lib.musl.general/11236 Path: news.gmane.org!.POSTED!not-for-mail From: Andre McCurdy Newsgroups: gmane.linux.lib.musl.general Subject: Re: [MUSL] microMIPS32R2 O32 port Date: Wed, 12 Apr 2017 14:47:20 -0700 Message-ID: References: <20170406161804.GM17319@brightrain.aerifal.cx> <20170407141941.GQ17319@brightrain.aerifal.cx> <20170412192535.GG2082@port70.net> <20170412202721.GY17319@brightrain.aerifal.cx> Reply-To: musl@lists.openwall.com NNTP-Posting-Host: blaine.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-Trace: blaine.gmane.org 1492033654 17765 195.159.176.226 (12 Apr 2017 21:47:34 GMT) X-Complaints-To: usenet@blaine.gmane.org NNTP-Posting-Date: Wed, 12 Apr 2017 21:47:34 +0000 (UTC) Cc: Jaydeep Patil To: musl@lists.openwall.com Original-X-From: musl-return-11251-gllmg-musl=m.gmane.org@lists.openwall.com Wed Apr 12 23:47:30 2017 Return-path: Envelope-to: gllmg-musl@m.gmane.org Original-Received: from mother.openwall.net ([195.42.179.200]) by blaine.gmane.org with smtp (Exim 4.84_2) (envelope-from ) id 1cyQ6r-0004Y2-Vu for gllmg-musl@m.gmane.org; Wed, 12 Apr 2017 23:47:30 +0200 Original-Received: (qmail 7876 invoked by uid 550); 12 Apr 2017 21:47:33 -0000 Mailing-List: contact musl-help@lists.openwall.com; run by ezmlm Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-ID: Original-Received: (qmail 7858 invoked from network); 12 Apr 2017 21:47:32 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=LPaHm0WByQIobUWNbBdA42jGqP+HfmBYyIUXl4IY1Wc=; b=Eb6RIxdzqS8OTx/OnpjYk/uxurwSBZ3Tv6cyNMQzLjb4jufe8thLzwaF7m7UIYg87L ioX/yX+h7e6+o0MU18z5VeggWHHKr3XvrrPU17+4iBNvQyUQQbhWoEBDrTAxkd3nqA2X Rnpm91g8Fht+qEhtWAmVrh2I24sbPtwCQ4wr07rTrkP0pQtKC4ulFaqxlPVI37YMm7Rt 7DFaQ+CU8ydhtdHzIVE7WR8oSAAU2xJDNDWVm3V2ra99ayV2m1XK7jf0TIPrOvYJmCwm +ojL2y/bnwU5AWublKc2+jP0cmcQUrMUV7JPJF7kuooL3O2DVCKC4hoKLEn6EgSOhaTT LXcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=LPaHm0WByQIobUWNbBdA42jGqP+HfmBYyIUXl4IY1Wc=; b=V3MC4QaE38rdOqF4dcQbg8o/Bmf7eDjSiEsWMaeco/w9j4Um0sK5Fx+1Fo5jgBeJqx uROTLebQpFVNnX09SRkpOI3Rmea3qr/acmvQLNtYhNf8N2hEocuneQn2TWiUS1Aw3+9X fXbVHK1PixIYMbAUQYuAyw7XyMalbupGf+i1iw6yUpVvSChgBOBvpjLSRXpZYcRwKQbv fJPkB4nhm6J8PFN1L/Ril3LzN1+4+tV9B796D8NdUMfNNgptT8IxHYmczgC0HUMoZUzr 1djsRTl43Pyk3EOPRFvDBCzQJrTUc7ggVtEs7mbLxURkou2QPwItpO2MRUtBX0u03oyy DOSQ== X-Gm-Message-State: AN3rC/650LtRv46VFqbLb7EcF2bmbr1LsENYFmf6Pe9axN19Xgkvwr+a h8BzleSBjZF2bZOeuB4hSeq///RyOLh7 X-Received: by 10.28.70.129 with SMTP id t123mr306779wma.98.1492033640902; Wed, 12 Apr 2017 14:47:20 -0700 (PDT) In-Reply-To: <20170412202721.GY17319@brightrain.aerifal.cx> Xref: news.gmane.org gmane.linux.lib.musl.general:11236 Archived-At: On Wed, Apr 12, 2017 at 1:27 PM, Rich Felker wrote: > On Wed, Apr 12, 2017 at 09:25:35PM +0200, Szabolcs Nagy wrote: >> * Jaydeep Patil [2017-04-12 11:54:10 +0000]: >> > Hi Rich, >> > >> > We can reuse existing MIPS code for microMIPS. There are places where = we read from $ra must be compiled for MIPS. >> > Please refer to https://github.com/JaydeepIMG/musl-1/tree/micromips32r= 2_v2 for modifications. >> > >> >> is micromips a different encoding for mips instructions >> that works on some cpus but not others? > > Yes, it's something like thumb or thumb2 on arm, or the riscv > compressed isa. What I'm not clear on is whether there are > micromips-only cpu models that can't execute normal mips. According to: https://imagination-technologies-cloudfront-assets.s3.amazonaws.com/docum= entation/MIPS_Architecture_microMIPS32_InstructionSet_AFP_P_MD00582_06.04.p= df "microMIPS is also an alternative to the MIPS=C2=AE instruction encoding and can be implemented in parallel or stand-alone." "If only one ISA mode exists (either MIPS or microMIPS) then this mode switch mechanism does not exist" > If so we probably need the ability to build musl as micromips, but as > long as cpus which support both support interworking (calls between > the two type of code in the same process) reasonably, I don't think > there's any reason to consider it a different subarch. > > If not (that is, if all cpus that support micromips also support the > normal mips isa) then I fail to see why there's any need to compile > musl's asm files as micromips. They're not size or performance > bottlenecks. > > Rich