From mboxrd@z Thu Jan 1 00:00:00 1970 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on inbox.vuxu.org X-Spam-Level: X-Spam-Status: No, score=-3.3 required=5.0 tests=MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL autolearn=ham autolearn_force=no version=3.4.4 Received: (qmail 15146 invoked from network); 7 Sep 2020 22:31:01 -0000 Received: from mother.openwall.net (195.42.179.200) by inbox.vuxu.org with ESMTPUTF8; 7 Sep 2020 22:31:01 -0000 Received: (qmail 13337 invoked by uid 550); 7 Sep 2020 22:30:56 -0000 Mailing-List: contact musl-help@lists.openwall.com; run by ezmlm Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-ID: Reply-To: musl@lists.openwall.com Received: (qmail 13319 invoked from network); 7 Sep 2020 22:30:56 -0000 X-Gm-Message-State: AOAM530D60DQ2EHA7XsNGmAMo1t7EeFtNQehZxmDfZwWJpu6CBtmAiYU 4wVP3Sk2kBmkOjG43RhG7CShxTkacPHiVUZkXxI= X-Google-Smtp-Source: ABdhPJyLmOhGvGVvAgTEf48xKvEAb7zxYQGIO34qgIH+GXtTJgOiSsP/NY+B17VaB4KZzB+H09r+J7w/z8LZZR7jrqA= X-Received: by 2002:aed:2414:: with SMTP id r20mr22754652qtc.304.1599517843459; Mon, 07 Sep 2020 15:30:43 -0700 (PDT) MIME-Version: 1.0 References: <68b5e735-45be-413f-8153-cb97dd5967cd@www.fastmail.com> <20200907180636.GM3265@brightrain.aerifal.cx> <20200907214554.GO3265@brightrain.aerifal.cx> <20200907221151.GP3265@brightrain.aerifal.cx> In-Reply-To: <20200907221151.GP3265@brightrain.aerifal.cx> From: Arnd Bergmann Date: Tue, 8 Sep 2020 00:30:27 +0200 X-Gmail-Original-Message-ID: Message-ID: To: musl@lists.openwall.com Content-Type: text/plain; charset="UTF-8" X-Provags-ID: V03:K1:tf6E+f69e6hwzvVaU6Wo+dNzITLC24kje3HC0oejuuysozTXz+e 0Nyt6p5+WB9C2juuenQnwFYKywP7rvR/RxqHG+iwg4kpkjUg9TyV6cOHqKkh6VXq+S5Q4aZ QXugZwd/XaxlxFE34b2Pc0wVnprVANPIllhJwACA5vPjNiuwIJ9UzawOcbCYUFPO8/eLXyv x9peZ4e8l4zClSuI4SPDQ== X-UI-Out-Filterresults: notjunk:1;V03:K0:oCMpWjlOnTw=:DOcVjAh2Q6oNYJp7KQlfoV wt6PzoSRLOv+2qhBOwdHvgHqT5ojdQw1W0u8Yz7iogoa5yDjIxgWmmrz0oo66rf5h491zkMbc M3VVrr12OLmuzBcXYxZqqikXGH/dbttS7fL/otvt4RgTRt5bKfUxBJLLuz+aTAKYN1HbKNFxW vFRlgdI5PmEoZW4n69t/Gwy9c1+bL6uMiFKMuvm4yl30kOooAduDHfGYkBbwBQQfkKHCS4bFY ipOSJ+/yCt0mafGRXr6QDgfygDDd19E9ZvD8LkOOXZNU08oOF1FH34eOh5F6oqHPM8DO/pV64 W5VYfJfNuUEzkSNWt7husW6iMC74cPHZPSA/5k4dm94Wxw2izWIEXTZ5TLm8UQQJVhkQBVU4w RGJU0zl5Qvot1LA3oG+fW8Y4bdjWspQ2v+K1HomjqlZSv1/G0P0mAYJ+7PNbuQ0CAe/Tloeap WPw7cIoGVGJ5nbt56MC/6UTgu0QRJGI2L1y3H+IrhpeZw2dv3cAALhFNieLYPyd5e4rjZOoHe hht0gcK+ZitSQhYT3If7AL3HrS5wpPLoeVlISf/KMeHvBMbnWYAiP3RJaWzF3cfHv7ffu8xC2 wr4qC9ijPfo19U//Q1dDNXGDgAU17BYlLyxJK9kl5rxJ4S8SlREWB6HoNQTenir4MNzfGRX7m DKg9QvjFq41G7D5oo4mt4EKCaZuJdOD5Uk2NcXqOwLt+zTIaYDKatdODBLGdwvswPpIAi7sEy JZ7iDvFA3KxWudL4tNgd2NCUDxmdpQue8jSZnSvJkJOp8yxzBctk1m/4rwihhmp1VVQeVO03y gYfuqNZWPO10kIr2Vb34MHScXaEMDuB9UIPUaLEz8RcqK6CrrpVsoqbO3tjz13Qc18WSrSM Subject: Re: [musl] riscv32 v2 On Tue, Sep 8, 2020 at 12:12 AM Rich Felker wrote: > As an aside, I should probably cleanup the current definition > framework where IPC_64==0x100 is the default and archs that want 0 > have to define it explicitly. It looks like, for the most part, IPC_64 > is needed iff SYS_ipc is defined. Right, there are no architectures that provide sys_ipc and want the flag to be zero. > Of the archs we support, arm > (32-bit) and mips{n32,64} seem to be the only ones that lack SYS_ipc > but need the IPC_64 bit set. Does this agree with your assessment? I think microblaze is in the same group. Note that for odd reasons it has always defined the __NR_ipc macro to 117 but hooked it up to -ENOSYS instead of sys_ipc in the kernel. I'm never quite sure whether we should treat that as a bug in the header file that we want to fix, or whether we should keep such constants around in new headers that were present in older ones. Arnd