From mboxrd@z Thu Jan 1 00:00:00 1970 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on inbox.vuxu.org X-Spam-Level: X-Spam-Status: No, score=-3.1 required=5.0 tests=DKIM_ADSP_CUSTOM_MED, DKIM_INVALID,DKIM_SIGNED,FREEMAIL_FROM,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 Received: (qmail 25819 invoked from network); 28 Jul 2023 16:47:19 -0000 Received: from second.openwall.net (193.110.157.125) by inbox.vuxu.org with ESMTPUTF8; 28 Jul 2023 16:47:19 -0000 Received: (qmail 26089 invoked by uid 550); 28 Jul 2023 16:47:15 -0000 Mailing-List: contact musl-help@lists.openwall.com; run by ezmlm Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-ID: Reply-To: musl@lists.openwall.com Received: (qmail 26051 invoked from network); 28 Jul 2023 16:47:14 -0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1690562822; x=1691167622; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=LAr5TNRBO8CYvTlIznHofshVqIwjyvqVztMs0gQDhh0=; b=YQhazoptv2KgsOSdytOf4Ysjj85qMU9QcCgegIYz83WcruZPr3v5vxO/rqZepoDxMQ vhaLSkCfPq0ryL7tQVUthvmUPlamTykO/rkATgfqbtmn5H80eGrZLIQMY+tA/qAjaE8V YZDq91hzSljXoZwz9YKEoOXq2Q3vV2e8oxDO1p2jVv+pNQ/7nADX9JQHIR6HvyZvBctC pPSHO6QAEtiiFTMGhm2qaCGPM5OT3uLb5r1aWdWcFYCGL2z8ZZlajeJ7hU2YQiC5qNxy gc+IeFFsl6W9URKMD/dvrI7SlbLJW3qRdwJWa/sH5zUnTGkozjHLBzfqKv352/AsNt9r PtFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1690562822; x=1691167622; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LAr5TNRBO8CYvTlIznHofshVqIwjyvqVztMs0gQDhh0=; b=TJCMpYb4pQ6Pqd6gpnBraWoIivKjd2ectj/LVRBlLCDQsEv3mavS8uuJcxDMOF7AMA AOoZaJiC1j4ZjyhmvfaEyByk5vIanZRpvpOeV8u1CrsPjOYdXabxtbBCqk4wGjQ5H0rH ujMLzqbLJ+Sa0S8W9JTUXzJgwS3SVDS3RhlPH+v2A+IXWCokv4RY+9/O19C3bBNjin4L bdOu4I/SD2c5dXhXnOkQuGAXFnl3Mg106rwPDuGeIZZZDIfWyybrNrl5mnqOOff4WriQ Oai8tEfKrIxPY2Ur487x+bqLoHKaTY/jRx98avgs5RgVt/XkZOr05AvJ3x9QvHFX9SF+ UZcQ== X-Gm-Message-State: ABy/qLaCuMRvRGVLyeOkFpnH5Mbv8YpRbjH+6ifw404/HJR8i85ZEQ7H vxP1z5JXrZ6zi3n2Q27G0DtRrQHfpBdTVhMAhyMWUt86hRU= X-Google-Smtp-Source: APBJJlF74yEurqzygnmZ2s20+WrbnBTH4290j8WH34PO1X3lTfng4tc8rV8353SUTFowpI/cSBmu1da7Nd55KiaFeb4= X-Received: by 2002:a05:6870:8192:b0:1bb:226d:cdb3 with SMTP id k18-20020a056870819200b001bb226dcdb3mr4131013oae.14.1690562821929; Fri, 28 Jul 2023 09:47:01 -0700 (PDT) MIME-Version: 1.0 References: <20230728061955.20156-1-zhang_fei_0403@163.com> <20230728061955.20156-2-zhang_fei_0403@163.com> In-Reply-To: <20230728061955.20156-2-zhang_fei_0403@163.com> From: Khem Raj Date: Fri, 28 Jul 2023 09:46:36 -0700 Message-ID: To: musl@lists.openwall.com Cc: dalias@libc.org, zhangfei Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Subject: Re: [musl] [PATCH 1/1] RISC-V: Add some mathematical functions to riscv64 On Thu, Jul 27, 2023 at 11:21=E2=80=AFPM zhangfei = wrote: > > From: zhangfei > > Add a series of function implementations such as lrint and lround. > Do you have some performance numbers with these implementations to share ? > Signed-off-by: Zhang Fei > --- > src/math/riscv64/llrint.c | 16 ++++++++++++++++ > src/math/riscv64/llrintf.c | 16 ++++++++++++++++ > src/math/riscv64/llround.c | 16 ++++++++++++++++ > src/math/riscv64/llroundf.c | 16 ++++++++++++++++ > src/math/riscv64/lrint.c | 16 ++++++++++++++++ > src/math/riscv64/lrintf.c | 16 ++++++++++++++++ > src/math/riscv64/lround.c | 16 ++++++++++++++++ > src/math/riscv64/lroundf.c | 16 ++++++++++++++++ > 8 files changed, 128 insertions(+) > create mode 100644 src/math/riscv64/llrint.c > create mode 100644 src/math/riscv64/llrintf.c > create mode 100644 src/math/riscv64/llround.c > create mode 100644 src/math/riscv64/llroundf.c > create mode 100644 src/math/riscv64/lrint.c > create mode 100644 src/math/riscv64/lrintf.c > create mode 100644 src/math/riscv64/lround.c > create mode 100644 src/math/riscv64/lroundf.c > > diff --git a/src/math/riscv64/llrint.c b/src/math/riscv64/llrint.c > new file mode 100644 > index 0000000..2b5ea25 > --- /dev/null > +++ b/src/math/riscv64/llrint.c > @@ -0,0 +1,16 @@ > +#include > + > +#if __riscv_flen >=3D 64 > + > +long long llrint (double x) > +{ > + long long res; > + __asm__ ("fcvt.l.d %0, %1" : "=3Dr" (res) : "f" (x)); > + return res; > +} > + > +#else > + > +#include "../llrint.c" > + > +#endif > diff --git a/src/math/riscv64/llrintf.c b/src/math/riscv64/llrintf.c > new file mode 100644 > index 0000000..d69566b > --- /dev/null > +++ b/src/math/riscv64/llrintf.c > @@ -0,0 +1,16 @@ > +#include > + > +#if __riscv_flen >=3D 32 > + > +long long llrintf (float x) > +{ > + long long res; > + __asm__ ("fcvt.l.s %0, %1" : "=3Dr" (res) : "f" (x)); > + return res; > +} > + > +#else > + > +#include "../llrintf.c" > + > +#endif > diff --git a/src/math/riscv64/llround.c b/src/math/riscv64/llround.c > new file mode 100644 > index 0000000..d6d2619 > --- /dev/null > +++ b/src/math/riscv64/llround.c > @@ -0,0 +1,16 @@ > +#include > + > +#if __riscv_flen >=3D 64 > + > +long long llround (double x) > +{ > + long long res; > + __asm__ ("fcvt.l.d %0, %1, rmm" : "=3Dr" (res) : "f" (x)); > + return res; > +} > + > +#else > + > +#include "../llround.c" > + > +#endif > diff --git a/src/math/riscv64/llroundf.c b/src/math/riscv64/llroundf.c > new file mode 100644 > index 0000000..72b343a > --- /dev/null > +++ b/src/math/riscv64/llroundf.c > @@ -0,0 +1,16 @@ > +#include > + > +#if __riscv_flen >=3D 32 > + > +long long llroundf (float x) > +{ > + long long res; > + __asm__ ("fcvt.l.s %0, %1, rmm" : "=3Dr" (res) : "f" (x)); > + return res; > +} > + > +#else > + > +#include "../llroundf.c" > + > +#endif > diff --git a/src/math/riscv64/lrint.c b/src/math/riscv64/lrint.c > new file mode 100644 > index 0000000..c62e306 > --- /dev/null > +++ b/src/math/riscv64/lrint.c > @@ -0,0 +1,16 @@ > +#include > + > +#if __riscv_flen >=3D 64 > + > +long lrint (double x) > +{ > + long res; > + __asm__ ("fcvt.l.d %0, %1" : "=3Dr" (res) : "f" (x)); > + return res; > +} > + > +#else > + > +#include "../lrint.c" > + > +#endif > diff --git a/src/math/riscv64/lrintf.c b/src/math/riscv64/lrintf.c > new file mode 100644 > index 0000000..6f3b120 > --- /dev/null > +++ b/src/math/riscv64/lrintf.c > @@ -0,0 +1,16 @@ > +#include > + > +#if __riscv_flen >=3D 32 > + > +long lrintf (float x) > +{ > + long res; > + __asm__ ("fcvt.l.s %0, %1" : "=3Dr" (res) : "f" (x)); > + return res; > +} > + > +#else > + > +#include "../lrintf.c" > + > +#endif > diff --git a/src/math/riscv64/lround.c b/src/math/riscv64/lround.c > new file mode 100644 > index 0000000..7d061e8 > --- /dev/null > +++ b/src/math/riscv64/lround.c > @@ -0,0 +1,16 @@ > +#include > + > +#if __riscv_flen >=3D 64 > + > +long lround (double x) > +{ > + long res; > + __asm__ ("fcvt.l.d %0, %1, rmm" : "=3Dr" (res) : "f" (x)); > + return res; > +} > + > +#else > + > +#include "../lround.c" > + > +#endif > diff --git a/src/math/riscv64/lroundf.c b/src/math/riscv64/lroundf.c > new file mode 100644 > index 0000000..34d978b > --- /dev/null > +++ b/src/math/riscv64/lroundf.c > @@ -0,0 +1,16 @@ > +#include > + > +#if __riscv_flen >=3D 32 > + > +long lroundf (float x) > +{ > + long res; > + __asm__ ("fcvt.l.s %0, %1, rmm" : "=3Dr" (res) : "f" (x)); > + return res; > +} > + > +#else > + > +#include "../lroundf.c" > + > +#endif > -- > 2.34.1 >