From mboxrd@z Thu Jan 1 00:00:00 1970 X-Msuck: nntp://news.gmane.org/gmane.linux.lib.musl.general/10197 Path: news.gmane.org!not-for-mail From: "Zhao, Weiming" Newsgroups: gmane.linux.lib.musl.general Subject: Re: build musl for armv7m Date: Wed, 22 Jun 2016 12:08:13 -0700 Message-ID: References: <805971fb5f9b1ee12edab9b7f3e86114@codeaurora.org> <20160614130036.GD10893@brightrain.aerifal.cx> <4858c023-2689-cec7-5335-15c33b8c8b92@codeaurora.org> <20160614163252.GQ22574@port70.net> <0e13c593-33fa-be67-5e73-cec7d7edfe15@codeaurora.org> <20160620195832.GN10893@brightrain.aerifal.cx> Reply-To: musl@lists.openwall.com NNTP-Posting-Host: plane.gmane.org Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="------------BF5C7E729E9E19D7532F7E04" X-Trace: ger.gmane.org 1466622517 28157 80.91.229.3 (22 Jun 2016 19:08:37 GMT) X-Complaints-To: usenet@ger.gmane.org NNTP-Posting-Date: Wed, 22 Jun 2016 19:08:37 +0000 (UTC) To: musl@lists.openwall.com Original-X-From: musl-return-10210-gllmg-musl=m.gmane.org@lists.openwall.com Wed Jun 22 21:08:32 2016 Return-path: Envelope-to: gllmg-musl@m.gmane.org Original-Received: from mother.openwall.net ([195.42.179.200]) by plane.gmane.org with smtp (Exim 4.69) (envelope-from ) id 1bFnVo-0002TU-AK for gllmg-musl@m.gmane.org; Wed, 22 Jun 2016 21:08:32 +0200 Original-Received: (qmail 8144 invoked by uid 550); 22 Jun 2016 19:08:29 -0000 Mailing-List: contact musl-help@lists.openwall.com; run by ezmlm Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-ID: Original-Received: (qmail 8117 invoked from network); 22 Jun 2016 19:08:27 -0000 X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.9 required=2.0 tests=ALL_TRUSTED,BAYES_00 autolearn=ham autolearn_force=no version=3.4.0 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.1.1 In-Reply-To: <20160620195832.GN10893@brightrain.aerifal.cx> Xref: news.gmane.org gmane.linux.lib.musl.general:10197 Archived-At: This is a multi-part message in MIME format. --------------BF5C7E729E9E19D7532F7E04 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Thanks for reviewing. I add tests for ARMv7m for memcpy. For atomics.s, I think the below are equivalent: ldr ip,1f ==> assembler will computes the offset from current inst to the label - ldr ip,[pc,ip] ==> here the address to be loaded is current PC + ip + add ip,pc,ip ==> here, the PC is the same as above + ldr ip,[ip] But I'm not familiar with the CP15 issue you mentioned. So, anyway, I skip the change for atomics.s in this patch. Thanks, Weiming On 6/20/2016 12:58 PM, Rich Felker wrote: > On Thu, Jun 16, 2016 at 11:34:28AM -0700, Zhao, Weiming wrote: >> I tried to build for armv6m (cortex-m0) and I got other build issues >> with .S and inline asms. >> >> Below are the changes for building armv7m: > I thought I'd already replied to this but I don't see my reply so I'm > doing it [again?] now. > >> diff --git a/src/setjmp/arm/longjmp.s b/src/setjmp/arm/longjmp.s >> index e28d8f3..e9b9b32 100644 >> --- a/src/setjmp/arm/longjmp.s >> +++ b/src/setjmp/arm/longjmp.s >> @@ -8,7 +8,9 @@ longjmp: >> mov ip,r0 >> movs r0,r1 >> moveq r0,#1 >> - ldmia ip!, {v1,v2,v3,v4,v5,v6,sl,fp,sp,lr} >> + ldmia ip!, {v1,v2,v3,v4,v5,v6,sl,fp} >> + ldr sp, [ip]! >> + ldr lr, [ip]! > I think changes like this are ok. They could be conditional on > __thumb__ if they hurt performance measurably on arm but I doubt it > matters. > >> diff --git a/src/string/arm/memcpy_le.S b/src/string/arm/memcpy_le.S >> index 4db4844..2517d15 100644 >> --- a/src/string/arm/memcpy_le.S >> +++ b/src/string/arm/memcpy_le.S >> @@ -241,7 +241,8 @@ non_congruent: >> beq 2f >> ldr r5, [r1], #4 >> sub r2, r2, #4 >> - orr r4, r3, r5, lsl lr >> + lsl r4, r5, lr >> + orr r4, r3, r4 >> mov r3, r5, lsr r12 >> str r4, [r0], #4 >> cmp r2, #4 > If this is in a hot path it may need to be conditional. > >> diff --git a/src/thread/arm/atomics.s b/src/thread/arm/atomics.s >> index 673fc03..a4bd03a 100644 >> --- a/src/thread/arm/atomics.s >> +++ b/src/thread/arm/atomics.s >> @@ -6,7 +6,8 @@ >> .type __a_barrier,%function >> __a_barrier: >> ldr ip,1f >> - ldr ip,[pc,ip] >> + add ip,pc,ip >> + ldr ip,[ip] >> add pc,pc,ip >> 1: .word __a_barrier_ptr-1b >> .global __a_barrier_dummy > As far as I can tell, this does not work at all. The arithmetic on pc > is assuming the particular offset between the instruction using pc and > the following code as arm opcodes. > > There's also the matter of the cp15 register load in this file that > doesn't exist on cortex-m. IMO the kernel (or bare-metal trap handler) > needs to trap and emulate it. > > Rich -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation --------------BF5C7E729E9E19D7532F7E04 Content-Type: text/plain; charset=UTF-8; name="patch.diff" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="patch.diff" diff --git a/src/setjmp/arm/longjmp.s b/src/setjmp/arm/longjmp.s index e28d8f3..e9b9b32 100644 --- a/src/setjmp/arm/longjmp.s +++ b/src/setjmp/arm/longjmp.s @@ -8,7 +8,9 @@ longjmp: mov ip,r0 movs r0,r1 moveq r0,#1 - ldmia ip!, {v1,v2,v3,v4,v5,v6,sl,fp,sp,lr} + ldmia ip!, {v1,v2,v3,v4,v5,v6,sl,fp} + ldr sp, [ip]! + ldr lr, [ip]! adr r1,1f ldr r2,1f diff --git a/src/setjmp/arm/setjmp.s b/src/setjmp/arm/setjmp.s index 8779163..fd380b0 100644 --- a/src/setjmp/arm/setjmp.s +++ b/src/setjmp/arm/setjmp.s @@ -9,7 +9,9 @@ __setjmp: _setjmp: setjmp: mov ip,r0 - stmia ip!,{v1,v2,v3,v4,v5,v6,sl,fp,sp,lr} + stmia ip!,{v1,v2,v3,v4,v5,v6,sl,fp} + str sp, [ip]! + str lr, [ip]! mov r0,#0 adr r1,1f diff --git a/src/string/arm/memcpy_le.S b/src/string/arm/memcpy_le.S index 4db4844..1137f55 100644 --- a/src/string/arm/memcpy_le.S +++ b/src/string/arm/memcpy_le.S @@ -241,7 +241,12 @@ non_congruent: beq 2f ldr r5, [r1], #4 sub r2, r2, #4 +#if (__ARM_ARCH_7A || __ARM_ARCH_7R || __ARM_ARCH > 7) orr r4, r3, r5, lsl lr +#else + lsl r4, r5, lr + orr r4, r3, r4 +#endif mov r3, r5, lsr r12 str r4, [r0], #4 cmp r2, #4 @@ -348,7 +353,12 @@ less_than_thirtytwo: 1: ldr r5, [r1], #4 sub r2, r2, #4 +#if (__ARM_ARCH_7A || __ARM_ARCH_7R || __ARM_ARCH > 7) orr r4, r3, r5, lsl lr +#else + lsl r4, r5, lr + orr r4, r3, r4 +#endif mov r3, r5, lsr r12 str r4, [r0], #4 cmp r2, #4 --------------BF5C7E729E9E19D7532F7E04--