From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on inbox.vuxu.org X-Spam-Level: X-Spam-Status: No, score=-3.0 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED,RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL autolearn=ham autolearn_force=no version=3.4.2 Received: from mother.openwall.net (mother.openwall.net [195.42.179.200]) by inbox.vuxu.org (OpenSMTPD) with SMTP id 14df2664 for ; Sun, 26 Jan 2020 03:28:52 +0000 (UTC) Received: (qmail 21662 invoked by uid 550); 26 Jan 2020 03:28:50 -0000 Mailing-List: contact musl-help@lists.openwall.com; run by ezmlm Precedence: bulk List-Post: List-Help: List-Unsubscribe: List-Subscribe: List-ID: Reply-To: musl@lists.openwall.com Received: (qmail 21643 invoked from network); 26 Jan 2020 03:28:50 -0000 X-Authentication-Warning: key0.esi.com.au: damianm owned process doing -bs Date: Sun, 26 Jan 2020 14:28:37 +1100 (AEDT) From: Damian McGuckin To: musl@lists.openwall.com In-Reply-To: <20200125001100.GY30412@brightrain.aerifal.cx> Message-ID: References: <20200118053759.GX30412@brightrain.aerifal.cx> <20200118094015.GE23985@port70.net> <20200124011122.GP30412@brightrain.aerifal.cx> <20200124045554.GR30412@brightrain.aerifal.cx> <20200124134402.GS30412@brightrain.aerifal.cx> <20200125001100.GY30412@brightrain.aerifal.cx> User-Agent: Alpine 2.02 (LRH 1266 2009-07-14) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; format=flowed; charset=US-ASCII Subject: Re: [musl] Considering x86-64 fenv.s to C M68K is below: I looked inside 'fenv.c' inside the .../fenv/arm directory and noticed it pulled in a default trivial 'fenv.c' from the directory above it. In the absence of an alternative, I might exploit that but say #include "../fenv-trivial.c" for that trivial case and #include "../fenv-generic.c" for the new generic architecture. Apologizing in advance for insuficient comments, but the hardware specific fenv.c for (say) the m68k is /* * 68k ARCHITECTURE * * this CPU has distinct control and status registers */ #include #if __HAVE_68881 || __mcffpu__ static inline unsigned int fe_get_sr_arch() { unsigned int v; __asm__ __volatile__ ("fmove.l %%fpsr,%0" : "=dm"(v)); return v; } static inline void fe_set_sr_arch(unsigned v) { __asm__ __volatile__ ("fmove.l %0,%%fpsr" : : "dm"(v)); } static inline unsigned int fe_get_cr_arch() { unsigned int v; __asm__ __volatile__ ("fmove.l %%fpcr,%0" : "=dm"(v)); return v; } static inline void fe_set_cr_arch(unsigned v) { __asm__ __volatile__ ("fmove.l %0,%%fpcr" : : "dm"(v)); } static inline unsigned int fe_get_ia_arch() { unsigned int address; __asm__ __volatile__ ("fmove.l %%fpiar,%0" : "=dm"(address)); return address; } static inline void fe_set_ia_arch(unsigned int address) { __asm__ __volatile__ ("fmove.l %0,%%fpiar" : : "dm"(address)); } /* * Expose the above generically */ #define fe_get_sr fe_get_sr_arch #define fe_set_sr fe_set_sr_arch #define fe_get_cr fe_get_cr_arch #define fe_set_cr fe_set_cr_arch /* * Handle the environment (which is a struct) */ #define fe_get_e(e)\ ((e)->__control_register = fe_get_cr_arch(),\ (e)->__status_register = fe_get_sr_arch(),\ (e)->__archnstruction_address = fe_get_ia_arch()) #define fe_set_e(e)\ (fe_set_cr_arch((e)->__control_register),\ fe_set_sr_arch((e)->__status_register),\ fe_set_ia_arch((e)->__instruction_address)) /* the contents of the default fenv_t */ #define FE_DFL_ENV_DATA { 0, 0, 0 } #include "../fenv-generic.c" #else #include "../fenv-trivial.c" #endif Regards - Damian Pacific Engineering Systems International, 277-279 Broadway, Glebe NSW 2037 Ph:+61-2-8571-0847 .. Fx:+61-2-9692-9623 | unsolicited email not wanted here Views & opinions here are mine and not those of any past or present employer