clz instruction is unavailable for Thumb1

clz instruction is unavailable for Thumb1

[Zhao, Weiming]

In arch/arm/atomic_arch.h, it checks for __ARM_ARCH >= 5, which is not 
sufficient.

for example, for armv6-m, it only support Thumb1, which doesn't include clz.

Suggest to check if it's building for thumb1:

diff --git a/arch/arm/atomic_arch.h b/arch/arm/atomic_arch.h
index c5c56f8..e3cb66a 100644
--- a/arch/arm/atomic_arch.h
+++ b/arch/arm/atomic_arch.h
@@ -82,7 +82,7 @@ static inline void a_crash()
                 : : : "memory");
  }

-#if __ARM_ARCH >= 5
+#if __ARM_ARCH >= 5 && !(defined(__thumb__) && !defined(__thumb2))



-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

Re: clz instruction is unavailable for Thumb1

[Andre McCurdy]

On Tue, Feb 27, 2018 at 4:03 PM, Zhao, Weiming <weimingz@codeaurora.org> wrote:
> In arch/arm/atomic_arch.h, it checks for __ARM_ARCH >= 5, which is not
> sufficient.
>
> for example, for armv6-m, it only support Thumb1, which doesn't include clz.
>
> Suggest to check if it's building for thumb1:

Musl does not currently support Thumb 1.

> diff --git a/arch/arm/atomic_arch.h b/arch/arm/atomic_arch.h
> index c5c56f8..e3cb66a 100644
> --- a/arch/arm/atomic_arch.h
> +++ b/arch/arm/atomic_arch.h
> @@ -82,7 +82,7 @@ static inline void a_crash()
>                 : : : "memory");
>  }
>
> -#if __ARM_ARCH >= 5
> +#if __ARM_ARCH >= 5 && !(defined(__thumb__) && !defined(__thumb2))
>
>
>
> --
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by
> The Linux Foundation
>

Re: clz instruction is unavailable for Thumb1

[Rich Felker]

On Tue, Feb 27, 2018 at 04:37:15PM -0800, Andre McCurdy wrote:
> On Tue, Feb 27, 2018 at 4:03 PM, Zhao, Weiming <weimingz@codeaurora.org> wrote:
> > In arch/arm/atomic_arch.h, it checks for __ARM_ARCH >= 5, which is not
> > sufficient.
> >
> > for example, for armv6-m, it only support Thumb1, which doesn't include clz.
> >
> > Suggest to check if it's building for thumb1:
> 
> Musl does not currently support Thumb 1.

I forget what the situation with v6-m is, and whether/how it could be
supportable. Is it really thumb1 or some thumb2 subset that fills
deficiencies? My recollection was that thumb1 lacks atomics, barriers,
thread-pointer loading, and maybe even syscalls, and since the
kuser_helper addresses are arm addresses, you can't even use them to
get the missing functionality.

Rich


> > diff --git a/arch/arm/atomic_arch.h b/arch/arm/atomic_arch.h
> > index c5c56f8..e3cb66a 100644
> > --- a/arch/arm/atomic_arch.h
> > +++ b/arch/arm/atomic_arch.h
> > @@ -82,7 +82,7 @@ static inline void a_crash()
> >                 : : : "memory");
> >  }
> >
> > -#if __ARM_ARCH >= 5
> > +#if __ARM_ARCH >= 5 && !(defined(__thumb__) && !defined(__thumb2))
> >
> >
> >
> > --
> > Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by
> > The Linux Foundation
> >

Re: clz instruction is unavailable for Thumb1

[Andre McCurdy]

On Tue, Feb 27, 2018 at 5:01 PM, Rich Felker <dalias@libc.org> wrote:
> On Tue, Feb 27, 2018 at 04:37:15PM -0800, Andre McCurdy wrote:
>> On Tue, Feb 27, 2018 at 4:03 PM, Zhao, Weiming <weimingz@codeaurora.org> wrote:
>> > In arch/arm/atomic_arch.h, it checks for __ARM_ARCH >= 5, which is not
>> > sufficient.
>> >
>> > for example, for armv6-m, it only support Thumb1, which doesn't include clz.
>> >
>> > Suggest to check if it's building for thumb1:
>>
>> Musl does not currently support Thumb 1.
>
> I forget what the situation with v6-m is, and whether/how it could be
> supportable. Is it really thumb1 or some thumb2 subset that fills
> deficiencies?

It's Thumb1 plus BL, DMB, DSB, ISB, MRS and MSR from Thumb2.

> My recollection was that thumb1 lacks atomics, barriers,
> thread-pointer loading, and maybe even syscalls, and since the
> kuser_helper addresses are arm addresses, you can't even use them to
> get the missing functionality.
>
> Rich
>
>
>> > diff --git a/arch/arm/atomic_arch.h b/arch/arm/atomic_arch.h
>> > index c5c56f8..e3cb66a 100644
>> > --- a/arch/arm/atomic_arch.h
>> > +++ b/arch/arm/atomic_arch.h
>> > @@ -82,7 +82,7 @@ static inline void a_crash()
>> >                 : : : "memory");
>> >  }
>> >
>> > -#if __ARM_ARCH >= 5
>> > +#if __ARM_ARCH >= 5 && !(defined(__thumb__) && !defined(__thumb2))
>> >
>> >
>> >
>> > --
>> > Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by
>> > The Linux Foundation
>> >

Re: clz instruction is unavailable for Thumb1

[Rich Felker]

On Tue, Feb 27, 2018 at 05:26:13PM -0800, Andre McCurdy wrote:
> On Tue, Feb 27, 2018 at 5:01 PM, Rich Felker <dalias@libc.org> wrote:
> > On Tue, Feb 27, 2018 at 04:37:15PM -0800, Andre McCurdy wrote:
> >> On Tue, Feb 27, 2018 at 4:03 PM, Zhao, Weiming <weimingz@codeaurora.org> wrote:
> >> > In arch/arm/atomic_arch.h, it checks for __ARM_ARCH >= 5, which is not
> >> > sufficient.
> >> >
> >> > for example, for armv6-m, it only support Thumb1, which doesn't include clz.
> >> >
> >> > Suggest to check if it's building for thumb1:
> >>
> >> Musl does not currently support Thumb 1.
> >
> > I forget what the situation with v6-m is, and whether/how it could be
> > supportable. Is it really thumb1 or some thumb2 subset that fills
> > deficiencies?
> 
> It's Thumb1 plus BL, DMB, DSB, ISB, MRS and MSR from Thumb2.

So that covers barrier but not atomics or thread pointer or syscalls,
right? I'm not seeing how arm with only thumb1 plus the above can be a
viable platform musl could run on, but maybe there are some kernel
mechanisms to help..?

Rich


> > My recollection was that thumb1 lacks atomics, barriers,
> > thread-pointer loading, and maybe even syscalls, and since the
> > kuser_helper addresses are arm addresses, you can't even use them to
> > get the missing functionality.
> >
> > Rich
> >
> >
> >> > diff --git a/arch/arm/atomic_arch.h b/arch/arm/atomic_arch.h
> >> > index c5c56f8..e3cb66a 100644
> >> > --- a/arch/arm/atomic_arch.h
> >> > +++ b/arch/arm/atomic_arch.h
> >> > @@ -82,7 +82,7 @@ static inline void a_crash()
> >> >                 : : : "memory");
> >> >  }
> >> >
> >> > -#if __ARM_ARCH >= 5
> >> > +#if __ARM_ARCH >= 5 && !(defined(__thumb__) && !defined(__thumb2))
> >> >
> >> >
> >> >
> >> > --
> >> > Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by
> >> > The Linux Foundation
> >> >

Re: clz instruction is unavailable for Thumb1

[Andre McCurdy]

On Tue, Feb 27, 2018 at 6:16 PM, Rich Felker <dalias@libc.org> wrote:
> On Tue, Feb 27, 2018 at 05:26:13PM -0800, Andre McCurdy wrote:
>> On Tue, Feb 27, 2018 at 5:01 PM, Rich Felker <dalias@libc.org> wrote:
>> > On Tue, Feb 27, 2018 at 04:37:15PM -0800, Andre McCurdy wrote:
>> >> On Tue, Feb 27, 2018 at 4:03 PM, Zhao, Weiming <weimingz@codeaurora.org> wrote:
>> >> > In arch/arm/atomic_arch.h, it checks for __ARM_ARCH >= 5, which is not
>> >> > sufficient.
>> >> >
>> >> > for example, for armv6-m, it only support Thumb1, which doesn't include clz.
>> >> >
>> >> > Suggest to check if it's building for thumb1:
>> >>
>> >> Musl does not currently support Thumb 1.
>> >
>> > I forget what the situation with v6-m is, and whether/how it could be
>> > supportable. Is it really thumb1 or some thumb2 subset that fills
>> > deficiencies?
>>
>> It's Thumb1 plus BL, DMB, DSB, ISB, MRS and MSR from Thumb2.
>
> So that covers barrier but not atomics or thread pointer or syscalls,
> right?

Thumb1 can make syscalls, but armv6-m has no atomics (the RTOS style
alternative being to disable interrupts around critical sections) and
no thread pointer (no coprocessors at all).

> I'm not seeing how arm with only thumb1 plus the above can be a
> viable platform musl could run on, but maybe there are some kernel
> mechanisms to help..?

I don't know if it's even possible to run a Linux kernel on these devices.

>> > My recollection was that thumb1 lacks atomics, barriers,
>> > thread-pointer loading, and maybe even syscalls, and since the
>> > kuser_helper addresses are arm addresses, you can't even use them to
>> > get the missing functionality.
>> >
>> > Rich
>> >
>> >> > diff --git a/arch/arm/atomic_arch.h b/arch/arm/atomic_arch.h
>> >> > index c5c56f8..e3cb66a 100644
>> >> > --- a/arch/arm/atomic_arch.h
>> >> > +++ b/arch/arm/atomic_arch.h
>> >> > @@ -82,7 +82,7 @@ static inline void a_crash()
>> >> >                 : : : "memory");
>> >> >  }
>> >> >
>> >> > -#if __ARM_ARCH >= 5
>> >> > +#if __ARM_ARCH >= 5 && !(defined(__thumb__) && !defined(__thumb2))
>> >> >

Re: clz instruction is unavailable for Thumb1

[Khem Raj]

On 2/27/18 5:01 PM, Rich Felker wrote:
> On Tue, Feb 27, 2018 at 04:37:15PM -0800, Andre McCurdy wrote:
>> On Tue, Feb 27, 2018 at 4:03 PM, Zhao, Weiming <weimingz@codeaurora.org> wrote:
>>> In arch/arm/atomic_arch.h, it checks for __ARM_ARCH >= 5, which is not
>>> sufficient.
>>>
>>> for example, for armv6-m, it only support Thumb1, which doesn't include clz.
>>>
>>> Suggest to check if it's building for thumb1:
>>
>> Musl does not currently support Thumb 1.
> 
> I forget what the situation with v6-m is, and whether/how it could be
> supportable. Is it really thumb1 or some thumb2 subset that fills
> deficiencies? My recollection was that thumb1 lacks atomics, barriers,
> thread-pointer loading, and maybe even syscalls, and since the
> kuser_helper addresses are arm addresses, you can't even use them to
> get the missing functionality.

v6-m doesn't have MMU IIRC, but it might be interesting as a FDPIC
platform.

Re: clz instruction is unavailable for Thumb1

[Szabolcs Nagy]

* Andre McCurdy <armccurdy@gmail.com> [2018-02-27 19:00:58 -0800]:
> On Tue, Feb 27, 2018 at 6:16 PM, Rich Felker <dalias@libc.org> wrote:
> > On Tue, Feb 27, 2018 at 05:26:13PM -0800, Andre McCurdy wrote:
> >> On Tue, Feb 27, 2018 at 5:01 PM, Rich Felker <dalias@libc.org> wrote:
> >> > I forget what the situation with v6-m is, and whether/how it could be
> >> > supportable. Is it really thumb1 or some thumb2 subset that fills
> >> > deficiencies?
> >>
> >> It's Thumb1 plus BL, DMB, DSB, ISB, MRS and MSR from Thumb2.
> >
> > So that covers barrier but not atomics or thread pointer or syscalls,
> > right?
> 
> Thumb1 can make syscalls, but armv6-m has no atomics (the RTOS style
> alternative being to disable interrupts around critical sections) and
> no thread pointer (no coprocessors at all).
> 
> > I'm not seeing how arm with only thumb1 plus the above can be a
> > viable platform musl could run on, but maybe there are some kernel
> > mechanisms to help..?
> 
> I don't know if it's even possible to run a Linux kernel on these devices.
> 

maybe this helps on linux:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=8fcd6c45f5a65621ec809b7866a3623e9a01d4ed