Re: [musl] [PATCH 0/1] riscv: Add support for Zacas in atomic operations

[Pincheng Wang <pincheng.plct@isrc.iscas.ac.cn>]

On 2025/9/19 00:47, Pincheng Wang wrote:
> Hi all,
> 
> This patch adds support for the RISC-V Zacas (Atomic Compare-and-Swap)
> extension in musl's atomic operations for both riscv64 and riscv32.
> 
> Currently, musl implements a_cas using a
> Load-Reserved/Store-Conditional (lr/sc) loop that:
> - Requires at least four instructions (lr+bne+sc+bnez) per CAS
>    operation,
> - Contains a retry loop under contention,
> - Incurs branch penalties that may cause pipeline stalls.
> 
> Zacas introduces amocas.w.aqrl/amocas.d.aqrl instructions that perform
> CAS atomically in a single instruction, eliminating retry loops and
> conditional branches.
> 
> Due to hardware limitations, we evaluated this change under QEMU using
> both mcycle and minstret counters. The results show clear benefits:
> 
> Metric											lr/sc	Zacas	Improvement
> Instr. per CAS (50k ops average)				15.04	8.36	-44.4%
> Instr. per op (single-thread)					23.61	14.25	-39.6%
> Instr. per op (multi-thread, high contention)	528.24	251.14	-52.5%
> 
> In addition, libc.a size is reduced by ~1.2% due to removal of loop
> code.
> 
> The patch automatically falls back to the lr/sc implementation on
> systems where Zacas is not available, preserving full backward
> compatibility.
> 
> This work provides a measurable reduction in instruction count,
> execution cycles and binary size, improving scalability of
> synchronization primitives under load.
> 
> Thanks for reviewing!
> 
> Best regards,
> Pincheng Wang
> 
> 
> Pincheng Wang (1):
>    riscv: add Zacas extension support for atomic CAS
> 
>   arch/riscv32/atomic_arch.h | 17 +++++++++++++++++
>   arch/riscv64/atomic_arch.h | 30 ++++++++++++++++++++++++++++++
>   2 files changed, 47 insertions(+)
> 

Hi all,

Friendly ping regarding my earlier patch on enabling the RISC-V Zacas 
(amocas.{w,d}) path for a_cas()/a_cas_p().

Best regards,
Pincheng Wang